AS1773 agreement

AS1773 was developed by the American Society of Automotive Engineers and is an enhanced version of MIL-STD-1773 [1]. It is now widely used in various fields such as aviation, aerospace and industrial control. The standard protocol processing part is almost the same as MIL-STD-1773. Only the transmission rate is changed to 20 Mbps, and a preamble is added before the status word / command word. Therefore, the two bus terminals AS1773 and MIL-STD-1773 can be implemented using the same protocol processing part.

Introduction to AS1773 protocol
There are three types of terminals on the 1773 bus: Bus Controller (BC), Remote Terminal (RT) and Bus Monitor (BM). All three terminals are connected to the bus to form a broadcast channel. Each terminal is usually connected to multiple buses at the same time, and one bus is selected as the main bus for normal communication, while the other buses are used as idle redundant buses. Once the main bus fails, all terminals switch to the redundant bus to continue Communicate. All terminals transmit information at a speed of 20 Mb / s on the bus, and up to 32 terminals can be connected on the bus [2].

Burst synchronization Generally speaking, data communication usually includes three forms of data formats, as shown in Figure 1. The first is continuous mode, where data is sent continuously, and the ratio of "1" and "0" is close to balance. The interval between two logical changes is strictly fixed, such as the 4B5B line code in point-to-point communication. The second is the burst mode, the ratio of "1" and "0" and the interval between the two logic changes are not strictly limited, such as the RS-232 interface of serial communication. The third is the mixed mode of report mode and burst mode. The amplitude value of different reports may be different, and there is a guard time between different reports. This type of data usually appears in the communication of message transmission, such as Ethernet. For burst synchronization, it is to synchronize the received burst data
[2]. Through the study of asynchronous transfer mode-passive optical network (Asynchronous Transfer Moder-Passive OpTIcal Network, ATM-PON), we can find that the burst synchronization of ATM-PON is similar to the burst synchronization of 1773 protocol, only in the format of the preamble There is a little difference. The preamble of ATM-PON includes preamble, guard time, power recovery BYTE, burst synchronization keyword, BYTE synchronization keyword, etc .; the preamble of 1773 is a "1" of 16 b. Therefore, based on the study of ATM-PON, it can be appropriately modified to meet the burst synchronization requirements of the 1773 protocol. For the burst synchronization of ATM-PON, there are mainly three methods of analog, gated oscillation, and multi-phase clock to synchronize the burst data. The three methods are described below.

Figure 1 Data format

The analog local clock signal and the data signal are integrated after limiting, in which the data signal is divided into two integrations, one is high level and the other is low level. The integrated signal of the clock and data is sent to the comparator. The difference value output by the comparator is sampled by the tracking and sampling circuit. The sampled value is used to control the voltage-controlled phase shifter, so that the input signal can be properly delayed to complete the synchronization process .
2.2 The schematic diagram of this method of gated oscillation is shown in Figure 2. The oscillating system includes 3 oscillators. A and B are used to synchronize input signals, and C is used to control A and B. The square wave frequency output by A and B should be consistent with the input frequency. Each oscillator is turned on or off as the signal changes, thereby achieving synchronization with the input signal. If the output frequency of the oscillator is the same as the frequency of the input signal, even if the signal has a long "0" or "1", it can be synchronized. In order to make the A and B oscillators consistent. You can use automatic tuning to introduce a main vibration C to make it run continuously, and use a phase-locked loop to keep it consistent with the external fixed reference frequency. The frequency calibration signal is shared by two slaves. So that the output clock meets the ideal requirements [3]. This memoryless system has a very important persistence, that is, when the gated oscillator is turned off, any phase errors accumulated due to oscillation cross-talk or transmission rate mismatch will be removed. This method requires a high level of process, and is not conducive to modification, and the cost is also high. For lower speed systems, this method is not cost-effective.

Figure 2 Block diagram of gated oscillation principle Figure 3 Block diagram of multiphase clock system

2.3 Multi-phase clock The traditional burst synchronizer mainly includes multi-phase clock and phase calibrator, correlator and selector. Figure 3 is a schematic diagram of burst synchronization based on a multiphase clock. The multiphase clock is generated by the multiphase clock generator, and the maximum phase difference of the multiphase clock is 360 Â°. At the same time, according to the relationship between the phase of each clock and the phase of the main clock, a certain delay is added to make each sampled data synchronized with the main clock. The sampled data enters the correlator, and the correlator passes the comparison result of the sampled data and the keyword to the selector. The selector selects the data that is most relevant to the keyword according to the correlation result of each data, and the output is restored Data and clock to achieve the purpose of burst synchronization [4]. This method has low development cost and short cycle, and is an ideal burst synchronization method for systems with low speeds, but for systems with relatively high speeds, it is suitable for Field Programmable Gate Array (FPGA). The requirements are quite high and difficult to achieve.

Design and implementation
3.1 Design principle The design module in this paper is composed of multi-phase clock generation circuit, multi-channel sampling circuit, phase adjustment circuit, discriminant search circuit, switch and output circuit. The multi-phase clock generation circuit generates four clock signals with a phase interval of 90 Â° and the same frequency as the OLT according to the input local clock Clk0, and then sends the four clock signals (Clk0, Clk1, Clk2, Clk3) to the multi-channel sampling circuit. The multi-channel sampling circuit uses these 4 clock signals to sample the serial data input by the burst to obtain 4 channels of data with different phases, which are sent to the phase adjustment circuit respectively. The phase adjustment circuit adjusts the four data with different phases to the Clk0 phase, and sends them to the discrimination search circuit and the switch circuit respectively. The discriminant search circuit searches for the preambles of the four data streams within a specified time. When "101" is detected in the three adjacent data streams, a control signal is generated and sent to the switching circuit to control the switching circuit Use the data of the middle phase as the recovered data. The output circuit is responsible for outputting the selected data and the corresponding Clk0 clock.
3.2 Specific implementation This article implements burst synchronization through the method of multi-phase clock, using FPGA of Cyclone EP1C6Q24C08 of Altera Company to realize burst synchronization circuit. As shown in Figure 4, the 40 MHz main clock signal forms four multiphase clock signals with a phase difference of 90 Â° through a phase-locked loop inside the FPGA. Sampling the input data separately, and adjusting the phase of the four-way sampling data so that their phases are all adjusted to Clk0. Then the search circuit performs a search of "101" on the sampled data, sees which clock gets "101" first, and then selects the middle data for output. That is, if Clk0 collects the data first, the Clk2 sampled data is output as the recovery data; if Clk1 collects the data first, the Clk3 sampled data is output as the recovery data; if Clk2 collects the data first, the Clk0 sampled data is used for recovery Data output; if Clk3 collects the data first, the data sampled by Clk1 is output as the recovered data. After the search circuit determines the optimal data as the recovered data, it generates a control signal and sends it to the selection output circuit. The output circuit outputs the optimally sampled data and clock through the serially sampled data stored in the register.

Burst synchronization design based on AS1773 protocol

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