Foreword
The design of high-speed analog-to-digital converters (ADCs) with high input frequency (IF) has proven to be a challenging task. The use of transformers makes this task even more difficult because of the inherent nonlinearities of the transformers, which can make performance difficult to meet standards. This paper classifies the problems that should be paid attention to when designing a transformer-coupled front-end for high-speed sub-ranging ADCs.
Design Parameters
There are several important parameters to consider when designing the front end.
The input impedance is the characteristic impedance of the design. In most cases it is 50Ω, but some designs require other impedance values. Transformers are essentially transimpedance devices because they can also achieve inter-circuit coupling with different characteristic impedances when necessary, allowing the overall system load to be adequately balanced.
Bandwidth is the range of frequencies used by the system. This width can be narrow or wide, distributed over the baseband (the first Nyquist frequency), or overlaid with multiple Nyquist zones.
The input drive level is a function of the bandwidth parameter that sets the system gain required for a particular application. The drive level is highly dependent on the front-end components used, such as filters and transformers, and this requirement is likely to be one of the most difficult parameters to achieve.
The voltage standing wave ratio (VSWR) measures the amount of power that is reflected into the load over the bandwidth of interest. This parameter sets the input drive level required to achieve full ADC input.
Passband flatness is the amount of performance fluctuations within a specified bandwidth. This may be due to the effects of ripple or the very slow roll-off characteristics of a simple low-pass filter. Passband flatness is often less than or equal to 1 dB, which is critical for overall system settings.
The signal-to-noise ratio (SNR) is the relative relationship between the signal seen by the converter and its own noise. In the front end, the SNR may be degraded due to bandwidth, signal quality (jitter), and gain. Keep in mind that when the signal is amplified, the noise component is also amplified at the same time.
Spurious Free Dynamic Range (SFDR) is the ratio of the full-scale rms value to the rms value of the peak parasitic spectral component. This is mainly due to the two characteristics of the front end. The first characteristic is the linearity of the transformer, or the balance quality, the latter is related to the second harmonic distortion; the second characteristic is the matching relationship between the gain and the input. As the amount of gain required increases, matching becomes more and more difficult, and the parasitic component of a nonlinear transformer (usually considered a 3rd harmonic) rises.
Transformer parameters
The transformer can be simply viewed as a bandpass filter.
Insertion loss, which represents the amount of loss the transformer has at a particular frequency, is the most common metric parameter in a transformer's data sheet, but it should not be the only indicator of design.
Return loss is the transformer seen on the primary side of the transformer when it is terminated. For example, an ideal 1:2 impedance converter with a 100Ω impedance at the secondary termination would have an impedance of 50Ω reflected in the primary stage. However, this is not always true because the impedance reflected by the primary side will change with frequency. As the impedance ratio increases, the return loss also changes accordingly.
Amplitude and phase imbalance is a key performance characteristic of the transformer. When the design needs to use an IF frequency above 100MHz, these two specifications allow the designer to understand how much nonlinearity may be encountered. As the frequency increases, the nonlinearity of the transformer also increases. The phase imbalance is often the main imbalance, which in turn leads to even-order distortion or an increase in the second harmonic.
ADC parameters
ADCs can be divided into two types: buffered and unbuffered. Unbuffered ADCs tend to consume much more power than buffered ADCs, but buffered ADCs are easier to drive.
A switched capacitor ADC is a specific example of an unbuffered ADC. The front-end design is directly connected to the internal sample-and-hold circuit (SAH) network of the ADC. This brings up two problems: First, the input impedance of the ADC changes with time and mode; the second is charge injection, which is reflected on the analog input of the ADC, which brings the filter Problems with filter settling.
The understanding and use of a buffered ADC is most convenient. The switching transient can be significantly reduced by using an isolation buffer that suppresses spikes caused by charge injection. Unlike in switched-capacitor ADCs, the termination characteristics of the input do not vary with the analog input frequency over the entire specified ADC bandwidth, and proper drive circuit selection becomes more convenient. The disadvantage of a buffered input stage is that it causes the ADC to consume more power.
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