Design and development of CAN bus communication based on S3C2410

1 Introduction

The networked control system is the development trend and research hotspot of the control system. As an important part of the networked system, the fieldbus control system has been widely used in actual control systems in recent years. CAN (Controller Area Network) bus is favored by users as a kind of field bus with strong fault tolerance, high reliability, simple wiring and low cost. The CAN bus has been widely used in China. At present, the widely used independent CAN controller SJA1000 in China often has low interface efficiency due to time-division multiplexing such as address and data bus; the number of receive and transmit buffers is too small, resulting in low data throughput; frame masking and filtering The setting of the filter is not flexible enough to meet the requirement of more shielding and filtering conditions at the same time.

The ARM chip S3C2410 is a highly integrated and cost-effective embedded processing chip that has been successfully used in industrial control equipment. However, the disadvantage is that there is no integrated CAN controller, which has hindered its application in industrial control products. In order to solve this problem, taking into account the complexity of the hardware circuit as much as possible and ensuring the stability and efficiency of CAN bus communication, an independent CAN controller MCP2515 with SPI interface is used to extend the CAN interface to the S3C2410. The following takes the design of the CAN bus communication interface in the self-developed human machine interface (HMI, Human Machine Interface) as an example.

2 CAN bus interface hardware design

The following briefly introduces the related controller chip, and then details the CAN interface hardware design.

2.1 Introduction to ARM chip S3C2410 and CAN controller MCP2515

S3C2410 is a 32-bit RISC embedded processor designed by Samsung. The chip is based on the ARM920T core and uses a five-stage pipeline and a Harvard structure to provide 1.1MIPS / MHz performance. In order to reduce the cost of application system design, S3C2410 integrates many common resources, such as: LCD controller, SDRAM controller, a touch screen interface, two SPI interfaces, etc., the maximum operating frequency of the core can reach 266MHz.

The independent CAN controller MCP2515's flexible interrupt capabilities, received frame masking and filtering, frame priority setting and other characteristics make it possible to manage information well, reducing the burden on the processor and the complexity of software design. Its unique features are as follows:

(1) There are two types of data frames: standard frame and extended frame. The length of the data field of each frame can be 0-8 bytes. The first two bytes of the data segment of the standard frame can be filtered separately;

(2) Contains 3 transmit buffers and 2 receive buffers, and its priority can be programmable;

(3) Contains 6 29-byte receive filters and 2 29-byte receive masks;

(4) With Loop-Back (self-loop detection) mode; support higher layer protocols, such as DeviceNet, SAEJ1939;

2.2 Hardware interface design

The SPI interface of S3C2410 is compatible with SPI V2.11 protocol and can support three data transfer modes of query, interrupt and DMA. The MCP2515 is connected to the SPI0 port of S3C2410, and their mutual connection relationship is shown in Figure 1.

Figure 1 PROFIBUS network characteristics

(1) This interface design does not use 5 pins such as TXnRTS, RXnBF, etc., and uses the total interrupt pin INT, so the corresponding function pins for sending requests and receiving interrupts are not enabled during software design, and are in this design This pin is not used for other purposes. After responding to the total interrupt, the processor accesses the corresponding register in the MCP2515 through the SPI interface to determine the specific interrupt event and handles it.

(2) In order to isolate the interference signal on the bus and improve the reliability of the system, an optical isolation is used between the CAN controller and the CAN transceiver. Separate power supplies should be used on both sides of the optical barrier, and they cannot directly share the ground with other parts of the system.

(3) Two equivalent resistors (R410, R411) and bypass capacitor (C408) are used between CANH and CANL to improve the performance of EME (Electro MagnaTIc Emission) and reduce the interference of this part to other parts of the system.

(4) During the initial 128 OSC clock cycles of the MCP2515 after initial power-on, reset, and wake-up from sleep mode, the OST (oscillation start timer) remains in the reset state. It should be noted that the SPI should not be operated before the OST times out.

(5) RX is designed to reduce EMI (Electro MagnaTIc Interference). The conversion rate of CANH and CANL is proportional to the current flowing through RX.

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