**Chen Xinglong, Tang Hai, Ren Peng, Li Jian, The 29th Institute of China Electronics Technology Corporation**
**Keywords:** I²C bus; FPGA; finite state machine; Verilog HDL
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**Introduction**
In modern communication systems, both serial and parallel buses are commonly used. Compared to parallel buses, serial buses offer advantages such as lower cost, fewer pin requirements, and simpler architectures. Among these, the I²C bus stands out due to its simplicity and practicality. Widely adopted in devices like serial EEPROMs, microcontrollers, and digital potentiometers, the I²C bus has become a staple in many embedded systems.
The I²C bus, short for "Inter-Integrated Circuit Bus," was originally developed by Philips (now NXP Semiconductors) in the Netherlands. It employs just two signal lines—SDA (data line) and SCL (clock line)—for bidirectional data transfer. These lines allow multiple ICs to connect to a single bus, each with its unique address for identification. This setup facilitates efficient data exchange between devices connected via the I²C bus.
While many I²C bus interface chips available today are dedicated hardware solutions, they often come with limited functionality and narrow address ranges. Leveraging the reprogrammability and debugging capabilities of FPGA technology, however, opens up new possibilities. By implementing the I²C bus design within an FPGA, developers can enhance versatility, reduce development time, and enable real-time configuration of bus functions.
**I²C Bus Data Transmission Protocol**
To ensure proper data transmission, the I²C bus must adhere to specific timing requirements. A complete data transmission sequence includes a start signal, address signal, read/write control signal, acknowledgment bit, data transmission, and a stop signal.
Here's how the I²C bus operates during data transfer:
1. Communication begins when the master generates a start condition by pulling the SDA line low while the SCL line remains high.
2. The master then transmits a 7-bit slave address followed by a read/write direction bit. A "0" indicates a write operation, while "1" signifies a read operation.
3. After the address and mode are sent, the slave responds with an acknowledgment bit. A low SDA level indicates an acknowledged response.
4. Subsequent data bytes are transferred byte-by-byte. During each cycle, the master sends data while the slave acknowledges receipt.
5. Finally, the master terminates communication by generating a stop condition, achieved by pulling the SDA line high while the SCL line remains high.
Common I²C operations include byte writes and random address reads. The respective timing diagrams for these operations are shown in Figures 2 and 3.
**Design of the I²C Bus**
The I²C bus interface comprises several key components: a register section, a clock generator, and an interface controller. The register section contains a status register, control register, transmission register, and reception register. The overall design is outlined in Figure 4.
The **control register** stores operational parameters such as the number of bytes to be read/written, operational modes, and status flags like start, reset, and acknowledge signals. The **status register** reflects the current state of the bus, enabling the host to monitor ongoing operations. The **transmission register** holds the data and addresses to be sent, while the **reception register** stores incoming data.
The **clock generator** ensures synchronized communication by producing the necessary clock pulses. The **interface controller**, acting as the core component, orchestrates all operations based on the I²C protocol.
**Finite State Machine Implementation**
The interface controller employs a finite state machine (FSM) to manage complex operations. The FSM transitions between states based on predefined rules, ensuring accurate execution of commands. Key states include the idle state, start state, address state, data transmission/reception states, and stop state.
For instance, upon receiving a start signal, the FSM transitions to the address state where the master sends the slave’s address and read/write mode. Depending on the operation type (e.g., byte write, random read), the FSM proceeds to subsequent states, managing acknowledgment signals and completing data exchanges.
**Verification and Application**
The designed I²C bus controller was tested with AT24C02 memory and AD5248 digital potentiometer. Simulation results confirmed compliance with the I²C communication standards. After downloading the firmware onto an FPGA, the controller demonstrated reliable communication and stable performance. Timing diagrams for byte write and random read operations are shown in Figures 6 and 7.
In practice, the I²C bus controller supports all five operating modes of the AT24C02 chip and can handle simultaneous read/write operations on digital potentiometers.
**Conclusion**
This paper outlines the implementation of an I²C bus controller using an FPGA and a finite state machine approach. The controller’s functionality was validated through AT24C02 experiments, confirming its compatibility with the I²C protocol. By leveraging FPGA’s flexibility, the design can be easily adapted for diverse applications, reducing development time and costs. Future work could explore additional optimizations and integration with larger systems.
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*Note: This document represents an enhanced version of the original text, rewritten for clarity and flow.*
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