Chen Xinglong, Tang Hai, Ren Peng, Li Jian, The 29th Institute of China Electronics Technology Corporation
Keywords: I2C bus; FPGA; finite state machine; Verilog HDL
Introduction
Communication buses currently in use can be categorized into two types: serial buses and parallel buses. Compared to parallel buses, serial buses are more cost-effective, require fewer pins, and have simpler structures. Among the various serial buses available, such as 1-Wire, IEEE1394, USB, and I2C, the I2C bus stands out due to its simplicity and practicality. It is widely used in devices like serial EEPROMs, microcontrollers, and digital potentiometers.
The I2C bus, short for Inter IC BUS, was initially developed by Philips of the Netherlands. It only requires two serial data lines for data transmission: the data line (SDA) and the clock line (SCL). These lines allow for bidirectional and binary data synchronous serial transmission. Multiple IC terminals can be connected on the bus, each with a unique address as an identifier. Each terminal can both send and receive data, enabling communication between connected IC terminals.
While many I2C-bus interface chips on the market today are dedicated chips, although they are affordable and user-friendly, their functionality is limited, and their versatility is low. The selectable address range is also small. With FPGA's programmable, easy-to-debug, and online reconfiguration features, selecting programmable devices to implement I2C bus design and applications can enhance the versatility of the I2C bus functions and significantly reduce the system development cycle.
1 I2C Bus Data Transmission Protocol
To ensure normal data transmission, the I2C bus must comply with the data transmission timing requirements specified in the I2C bus data transmission protocol. A complete data transmission timing requirement for the I2C bus is shown in Figure 1.
Figure 1 I2C Bus Complete Data Transmission Sequence
The I2C bus uses a clock synchronization signal to achieve synchronous data transmission. The signals related to data transmission mainly include a start signal, an address signal, a read/write control signal, an acknowledgment signal, a data transmission signal, and a stop signal.
The I2C bus operation sequence is described as follows:
(1) When communication begins, the master generates a start signal by pulling the data line (SDA) low while the clock line (SCL) is high.
(2) The master sends a 7-bit address and 1-bit read/write mode information to the slave. The first 7 bits determine which slave the master is communicating with, and the last bit indicates whether the master is sending or receiving data ("0" for sending, "1" for receiving).
(3) The next clock pulse is the response bit. The slave that matches the master's address will generate an acknowledge signal. A low SDA indicates an acknowledgment, while a high SDA indicates no acknowledgment.
(4) Data communication then occurs between the master and slave. Data transfer begins when SCL is low, and data communication officially happens when SCL goes high. After each byte of data is transmitted, the receiver must respond to confirm successful receipt.
(5) To terminate communication, the master pulls SDA high while SCL is high.
In the I2C bus data transmission process, typical read and write methods include byte write and random address read. The timing diagrams for these methods are shown in Figures 2 and 3, respectively.
Figure 2 Byte Write Timing
Figure 3 Random Address Read Timing
2 I2C Bus Design
2.1 Overall Block Diagram Design of the I2C Bus Interface
The I2C bus interface can be divided into three sections based on different functions: a register section, a clock generator section, and an interface controller section. The register section includes a status register, a control register, a transmission register, and a reception register. The overall block diagram is shown in Figure 4.
Figure 4 Overall Block Diagram of the I2C Bus Interface
The control register primarily stores the control signals, allowing the host computer to control the I2C bus interface. It consists of two 8-bit registers. One register stores the number of bytes to be read or written (WRcnt), while bits 0 to 4 of the register store the five operating modes: 00001 for byte write, 00010 for page write, 00100 for immediate address read, 01000 for random address read, and 10000 for sequential address read. Bit 5 stores the read/write status signal WR, bit 6 stores the start signal Start, and bit 7 stores the reset signal Reset.
The status register mainly stores the working status of the bus. Using the status register, the host can obtain real-time status information about the I2C bus interface. The lowest bit of the status register indicates that data can be read from the receive register (Data_Read_Ok), and the second highest bit indicates that data can be written to the transmit register (Data_Write_Ok).
The transmission register primarily stores the data and addresses to be sent. The address stored in the transmission register includes the slave address (Slave_Addr) and the byte address (Word_Addr).
The receive data register stores the data read from the I2C bus. The host can read the received data through this register.
The clock generator is used for generating the I2C bus interface controller clock.
The I2C interface controller is the core of the bus design. The main functions of the I2C bus are realized through the interface controller.
2.2 I2C Interface Controller
The I2C interface controller is the heart of the design and the most challenging part. The I2C interface controller needs to read and write data from/to the slave, and it must generate clock (SCL) and data (SDA) signals that meet the control timing requirements based on the information in the control register. Since the correctness of the control sequence directly affects the reliability of the control, a finite state machine can be used to design the interface controller. The I2C bus timing control diagram is shown in Figure 5.
Figure 5 I2C Bus Timing State Transition Diagram
The idle state of the finite state machine is idle. When a reset signal (Reset=0) is received, the state machine enters the idle state. After the FPGA issues the start (St=1) command, the state machine moves to the Start state, issuing the start signal on the clock line (SCL) and data line (SDA). The state machine then reaches the TAddr state, where the host sends the device address and read/write mode information to the slave. Once the output is complete, the host receives the reply signal from the slave, and the state machine transitions to the corresponding state based on different working mode requirements. For instance, byte write and page write also require the output of the slave’s byte address, and the response signal will only enter the write state. Random read requires outputting the start signal and the slave’s device address again, entering the read state after the address is sent. Immediate address reads and sequential reads do not require the output of the byte address to enter the read state.
The data write mode can implement byte write and page write. After writing a byte of data, it will receive a response signal from the slave. If all the bytes to be written have been written, the state machine enters the Stop state; otherwise, it continues to write the next byte. The data read mode enables immediate address reads, random reads, and sequential address reads. After reading a byte of data, a response signal is sent. If all the bytes to be read have been read, the state machine enters the Stop state; otherwise, the reading of the next byte continues.
After the state machine enters the Stop state, a stop signal is sent on the clock line (SCL) and the data line (SDA), and then the state machine enters the idle state.
2.3 I2C Interface Controller State Machine Code Design
The entire I2C interface controller state machine is composed of ten functional modules. By converting between these modules, specific functions are implemented. The start module, end module, send data module, and receive data module are basic modules. Due to space constraints, the following is only the program code for implementing the above four basic module functions using Verilog HDL language. The declaration of the relevant variables is omitted here.
(1) Start Module
This module is mainly used to initiate bus communication control. When the clock bus (SCL) is high, the data bus (SDA) level changes from high to low, initiating bus communication. The code is described as follows:
Start:
Begin
Count=count+1;
Case(count)
1: SDA<=1;
2: SCL<=1;
3: SDA<=0;
4: SCL<=0;
5:
Begin
Count=0;
State<=TAddr;
End
Default: state<=Idle;
Endcase
End
(2) End Module
This module is mainly used to stop bus communication control. When the clock bus (SCL) is high, the data bus (SDA) level changes from low to high, stopping the bus communication. The code is described as follows:
Stop:
Begin
Count=count+1;
Case(count)
1: SDA<=0;
2: SCL<=1;
3: SDA<=1;
4:
Begin
Count=0;
State<=Idle;
End
Default: state<=Idle;
Endcase
End
(3) Send Data Module
The send data module mainly implements the function of writing data to the slave. Each time a byte of data is written, when the number of bytes to be written is large, the module will be called repeatedly until all data is written from the machine. The code is described as follows:
TData:
Begin
Count=count+1;
Case(count)
1: SDA <= data_write[bcnt];
2: SCL<=1;
3: SCL<=0;
4:
Begin
If(bcnt==0)
Begin
Bcnt=8;
Data_write_ok=1;
TRcnt=TRcnt-1;
State<=TAck;
End
Else
State<=TData;
Bcnt=bcnt-1;
Count=0;
End
Default: state<=Idle;
Endcase
End
(4) Receive Data Module
The receiving data module mainly implements the function of reading data from the slave and completes the reading of one byte of data each time. When the number of bytes to be read is large, the module will be called repeatedly until all the data are read from the slave. The code is described as follows:
RData:
Begin
Count=count+1;
Case(count)
1: SDA<=1'bz;
2: SCL<=1;
3: data_read[bcnt]=SDA;
4: SCL<=0;
5:
Begin
If(bcnt==0)
Begin
Bcnt=8;
TRcnt=TRcnt-1;
State<=RAck;
Data_read_ok=1;
End
Else
State<=RData;
Bcnt=bcnt-1;
Count=0;
End
Default: state<=Idle;
Endcase
End
3 I2C Bus Application
In our experiments, we verified the function of the I2C bus controller with the simulation timing of the AT24C02 memory chip reading and writing data. The simulation timing results met the I2C communication standard. After downloading the program to the FPGA chip and running it, the communication data was correct, and the circuit was stable and reliable. The I2C bus controller program underwent logic synthesis in the Xilinx ISE 10.1 environment and used ModelSim 6.2b for communication timing simulation. The simulation diagrams are shown in Figures 6 and 7.
Figure 6 Simulation Timing Waveform of Byte Write Mode
Figure 7 Simulation Timing Waveforms for Random Address Read Operation Mode
Figure 6 is the simulation waveform diagram showing the host writing data, mainly realizing the byte write sequence simulation of the AT24C02 memory. The simulation in the figure is writing 1 byte of data AAH to a memory cell with a device address of 50H and a byte address of 03H. From the timing relationships in the simulation, it can be seen that the host correctly writes the slave address and data, along with the timing of the slave's response signal.
Figure 7 shows the simulation waveform of the host randomly reading data from the slave. It mainly simulates the random address reading of the AT24C02 memory. The simulation process reads out the previously written 1-byte data, and the read result matches exactly what was written. From the timing relationships in the simulation, it can be seen that the host correctly writes the slave address, reads the data, and the timing of the master acknowledgment signal is correct.
In practical applications, the I2C bus controller can implement read and write operations on the five operating modes of the AT24C02 chip and can simultaneously perform data read and write operations on the AD5248 digital potentiometer.
4 Conclusion
Based on the I2C bus communication protocol, this paper designs the I2C controller in a state machine mode and analyzes some basic modules. At the same time, the timing of the read/write status of the controller is verified using the AT24C02 chip. The results show that the I2C bus signal complies with the I2C communication standard, and downloading to the FPGA can fully realize the reading and writing of the chip with the I2C communication protocol.
Due to the flexibility of FPGA field programmable features in programming and debugging, the design can generate an IP core and embed it into an FPGA-based system design that can read and write IC chips in the I2C bus. This avoids the repeated development of different products and improves the design efficiency of the system. It reduces product development cycles and costs.
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