1 Introduction
With the deepening of the information technology revolution and the rapid development of computer technology, DSP technology is also being applied to various fields of science and technology and the national economy at an extremely fast speed. In many engineering development and design, because it is required to realize the communication between single-chip DSP and single-chip DSP, multi-chip DSP chips and other processing chips, how to realize these communications more efficiently and conveniently has become the majority of DSP applications One problem that the author must first solve.
This article introduces and discusses the configuration of TMS320C5402 DSP's multi-channel buffered serial port McBSP (MulTI-channel Buffered Serial Port) as SPI based on the author's experience in communicating with TI's DSP TMS320C5402 and NEC's μPD780308 microcontroller in engineering applications and debugging Mode (that is, the clock stop mode), so as to realize the communication design method between DSP and other single-chip processors. At the same time, some program codes of the implementation method are given.
2 Multi-channel buffered serial port McBSP
The function of the multi-channel buffered serial port McBSP is to provide serial exchange of data inside and outside the device. Compared with previous serial ports, McBSP serial ports have considerable flexibility. Table 1 gives the McBSP pin description about TMS320C5402. Among them, the serial port receiving and sending clock and synchronization frame signal can be provided by both external equipment and internal clock generator, which greatly improves the flexibility of communication.
Table 1 Description of the McBSP pins of TMS320C5402
Pin description
DR data input
DX data output
CLKR receive data bit clock
CLKX send data bit clock
FSR receive data frame clock
FSX send data frame clock
Clock source of sample rate generator provided externally by CLKS
3 McBSP clock stop mode in SPI protocol
The SPI protocol works in a master-slave mode. This mode usually has a master device and one or more slave devices. Its interface includes the following four signals:
(1) Serial data input (also known as master in, slave out, or MISO);
(2) Serial data output (also known as master output, slave input, or MOSI);
(3) Serial shift clock (also called SCK);
(4) Slave enable signal (also called SS).
Figure 1 is a schematic diagram of the SPI interface of the device. When the interface is working, the master device controls the flow of information by providing a shift clock and a slave enable signal. The slave enable signal is an optional high and low level, which can activate the serial input and output of the slave device (in the absence of a clock). In the absence of a dedicated slave enable signal, the communication between the master and slave devices is determined by the presence or absence of the shift clock. In this connection mode, the slave device must remain active from beginning to end, and the slave device can only It is one, not more than one.
The clock stop mode provided by TMS320C5402 can be used for SPI protocol communication. When McBSP is configured in clock stop mode, the transmitter and receiver are internally synchronized, that is, the transmit data frame clock (FSX) can be used as a slave enable (ie SS), and the transmit data bit clock (CLKX) is used as the SCK in the SPI protocol. Since the received data bit clock (CLKR) and received data frame clock (FSR) are internally connected to FSX and CLKX, this pin cannot be used in SPI mode.
When McBSP is configured as a master device, the transmit output signal (BDX) is used as the MOSI signal of the SPI protocol, and the receive input signal (BDR) is used as the MISO signal. Figure 2 shows the schematic diagram of the SPI interface when McBSP is used as the master device.
Similarly, when McBSP is configured as a slave device, BDX is used as the MISO signal, and BDR is used as the MOSI signal. Figure 3 is a schematic diagram of the SPI interface of McBSP used as a slave device.
When McBSP of TMS320C5402 is used in clock stop mode, the CLKSTP bit field of register SPCR1 and the CLKXP bit configuration of the pin configuration register are listed in Table 2.
Table 2 Clock stop mode configuration
Description of CLKSTPCLKXP
0XX is not available in clock stop mode. Clock is activated for non-SPI mode
100 clock starts on rising edge (no delay)
110 clock starts on rising edge (with delay)
101 clock starts on the falling edge (no delay)
111 clock starts on falling edge (with delay)
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