ApTIna’s AP0100CS Image Signal Processor (ISP) co-chip is specifically designed to work with CMOS image sensors, targeting the high-performance analog closed-circuit television (CCTV) market. As TV line resolution continues to evolve towards 650 TVL/PH and wide dynamic range (WDR) performance reaches up to 120 dB, the demand for higher resolution and broader dynamic range in CCTV systems is growing rapidly. The AP0100CS, when paired with ApTIna’s industry-leading low-light CMOS sensors, delivers advanced CCTV camera solutions that support both standard dynamic range (SDR) and wide dynamic range (WDR) imaging.
This powerful ISP integrates ApTIna’s cutting-edge image processing pipeline, offering exceptional video quality and strong low-light performance. With its Advanced Local Tone Mapping (ALTM) technology, the AP0100CS ensures high-quality video output even in challenging lighting conditions with extreme contrast. Additionally, the AP0100CS features an NTSC/PAL encoder with advanced conversion capabilities, enabling it to meet the high-resolution requirements of the CCTV market.
**Key Features:**
- Supports up to 1.2 Mp (1280x960) Aptina sensors
- 45 fps at 1.2 Mp, 60 fps at 720p
- Optimized for use with HDR sensors
- Color and gamma correction
- Auto exposure, auto white balance, 50/60 Hz auto flicker detection and avoidance
- Adaptive Local Tone Mapping (ALTM)
- Programmable Spatial Transform Engine (STE)
- Pre-rendered Graphical Overlay
- Two-wire serial programming interface (CCIS)
- SPI bus interface for low-cost Flash or EEPROM (for configuration and patch loading)
- High-level host command interface
- Standalone operation support
- Up to 5 GPIOs
- Fail-safe IO
- Multi-Camera synchronization support
- Integrated video encoder for NTSC/PAL with overlay capability and 10-bit I-DAC
**Key Performance Parameters:**
[Image: AP0100CS Image Signal Processor Introduction]
**Applications:**
- IP cameras and CCTV – HD
- Enables CCTV-HD with MP sensors
On the host side, a two-wire serial interface is used to control the AP0100CS, while image data is transferred via an analog or parallel interface between the AP0100CS and the host. The AP0100CS also connects to the sensor using a parallel interface.
**Figure 1: Typical Parallel Configuration**
The figure on page 7, “Typical Parallel Configuration,†and Figure 3, “Typical HiSPi Configuration,†on page 8 illustrate common device connections for the AP0100CS. All power supply rails should be decoupled from ground using capacitors placed as close as possible to the package.
The AP0100CS allows signals to the sensor and host interfaces to operate at different supply voltage levels, optimizing power consumption and enhancing flexibility. Table 1 on page 9 provides detailed signal descriptions for the AP0100CS.
[Image: AP0100CS Image Signal Processor Introduction]
**Figure 2: Typical Parallel Configuration**
Note:
1. This configuration represents just one of many possible variations.
2. ApTIna recommends a 1.5kΩ resistor for the two-wire serial interface; larger values may be used for slower speeds.
3. RESET_BAR has an internal pull-up and can be left floating if not used.
4. Decoupling capacitors for regulator input and output should be 1.0uF ceramic capacitors with X5R or X7R dielectric.
5. TRST_BAR should be connected to GND during normal operation.
6. ApTIna suggests placing 0.1μF and 1μF decoupling capacitors close to each power pin, depending on layout and design.
**Typical HiSPi (High Speed Serial Pixel Interface) Configuration:**
[Image: AP0100CS Image Signal Processor Introduction]
**Figure 3: Typical HiSPi Configuration**
**HiSPi and Parallel Connection:**
When using the HiSPi interface, connect the parallel interface to VDDIO_S. When using the parallel interface, the HiSPi interface and its power supply (VDD_PHY) can be left unconnected.
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