ApTIna's AP0100CS Image Signal Processor (ISP) co-chip is specifically designed to work with CMOS image sensors, targeting the high-performance analog closed-circuit television (CCTV) market. As TV line resolution (TVL) continues to increase towards 650 TVL/PH and wide dynamic range (WDR) performance reaches up to 120 dB, the demand for higher resolution and broader dynamic range in CCTV systems is growing rapidly. The AP0100CS, when paired with ApTIna’s leading low-light CMOS sensor technology, delivers high-resolution CCTV camera solutions that support both standard dynamic range (SDR) and wide dynamic range (WDR) applications.
This powerful ISP integrates ApTIna’s advanced image processing pipeline, delivering exceptional video quality and performance in low-light conditions. Its key feature, Advanced Local Tone Mapping (ALTM), ensures high-quality video output even under extreme lighting conditions with high contrast. Additionally, the AP0100CS includes an NTSC/PAL encoder with advanced conversion capabilities, enabling it to meet the high TV line resolution requirements of traditional CCTV systems.
**Key Features:**
- Supports up to 1.2Mp (1280x960) Aptina sensors
- Up to 45 fps at 1.2Mp and 60 fps at 720p
- Optimized for use with HDR sensors
- Color and gamma correction
- Auto exposure, auto white balance, and 50/60 Hz auto flicker detection
- Adaptive Local Tone Mapping (ALTM)
- Programmable Spatial Transform Engine (STE)
- Pre-rendered graphical overlay support
- Two-wire serial programming interface (CCIS)
- SPI bus interface for Flash or EEPROM configuration
- High-level host command interface
- Standalone operation capability
- Up to 5 GPIOs and fail-safe IO
- Multi-camera synchronization support
- Integrated NTSC/PAL video encoder with overlay and 10-bit I-DAC
**Applications:**
- IP cameras and CCTV – HD
- Enables CCTV-HD with multi-pixel sensors
On the host side, a two-wire serial interface controls the AP0100CS, while image data is transferred via analog or parallel interfaces between the AP0100CS and the host. The sensor interface also uses a parallel connection.
Figure 1 shows a typical parallel configuration, while Figure 2 illustrates a typical HiSPi configuration. These diagrams provide insights into common device connections for the AP0100CS.
When designing with the AP0100CS, all power supply rails should be decoupled from ground using capacitors placed as close as possible to the package. The signals between the AP0100CS, sensor, and host can operate at different voltage levels to optimize power consumption and enhance flexibility.
Table 1 on page 9 lists the signal descriptions for the AP0100CS. It is important to note that the typical configurations shown are just one of many possible variations. For the two-wire serial interface, ApTIna recommends a 1.5kΩ pull-up resistor, though higher values may be used for slower transmission speeds. RESET_BAR has an internal pull-up and can be left floating if not in use. Decoupling capacitors for the regulator input and output should be 1.0μF ceramic capacitors with X5R or X7R dielectric.
For HiSPi interface usage, the parallel interface should be connected to VDDIO_S, and the HiSPi interface and power supply (VDD_PHY) can be left floating when using the parallel interface. Proper decoupling capacitors (0.1μF and 1μF) should be placed as close as possible to each power pin, with actual values depending on the design and layout.
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