Abstract: A hybrid high dynamic range AGC algorithm is proposed for receiver applications. The algorithm integrates RF feedforward and IF feedback techniques, implemented using a field-programmable gate array (FPGA). Under the control of this algorithm, with key components such as an RF switch, digitally controlled attenuator, detector, and variable gain amplifier (VGA), an automatic gain control loop is realized. This system achieves an input dynamic range of 110 dB, a sensitivity of -100 dBm, and an output power of -19 dBm.
0. Preface
Due to factors like multipath fading, signal power at the antenna end of a receiver can fluctuate by more than 60 dB [1]. The fixed dynamic range of the intermediate frequency (IF) analog-to-digital converter (ADC) is insufficient to accurately sample such large variations in signal strength. To ensure correct demodulation and decoding in the baseband, the receiver must automatically adjust its gain based on the input signal strength, maintaining a stable output for subsequent stages. This functionality is achieved through an Automatic Gain Control (AGC) loop.
Commonly used AGC loops are categorized into three types: feedforward AGC, feedback AGC, and hybrid AGC [2-4]. Feedforward AGC operates in an open-loop configuration, where the input signal power is detected and used for gain adjustment. Feedback AGC uses a closed-loop structure, comparing the output power with a reference value to determine the gain adjustment. Research in [3] shows that feedforward AGC offers faster response times and simpler implementation, making it widely adopted. However, due to its sensitivity, feedforward AGC may misalign due to circuit parameter fluctuations. Feedback AGC provides more stable control but requires careful tuning of loop parameters, which complicates design. Hybrid AGC combines both approaches, offering the benefits of both feedforward and feedback systems.
1. Hybrid AGC Loop
The hybrid AGC loop in the receiver employs both RF feedforward and IF feedback circuits. As shown in Figure 1, the received signal is coupled into the RF detector. The detector's output voltage is converted to digital form via ADC and processed by the FPGA through a single-pole double-throw switch and a digitally controlled attenuator, which adjusts the RF section's gain. The Low Noise Amplifier (LNA) has a gain of 22 dB, while the attenuation network provides -10 dB. The RF signal is mixed with a local oscillator to produce an IF input signal (IFIN), which is amplified by two stages of VGA. The IF signal is then fed to the IF detector through a coupler, and the output voltage (VIFDET) is converted back to digital form for processing by the FPGA. The result determines the DAC output voltage, which controls the VGA gain. IFOUT represents the IF output signal, and VG is the VGA control voltage.
[Image: RF/IF AGC Block Diagram]
2. AGC Algorithm
Before introducing the AGC algorithm, the loop’s design specifications are outlined. The algorithm must handle two types of input signals: constant envelope and non-constant envelope. For constant envelope signals, the AGC control time should be less than 50 μs, with an input dynamic range of at least -95 dBm to +5 dBm and an output power of -19 dBm. For non-constant envelope signals, the output envelope must remain undistorted.
Based on these requirements, the overall algorithm shown in Figure 2 is designed. The system first detects whether the input signal is a constant envelope signal. If so, the fast AGC algorithm is executed; otherwise, the slow AGC algorithm is used. The process alternates between RF and IF AGC, repeating after a certain interval.
[Image: AGC Algorithm Flowchart]
The RF feedforward AGC algorithm is illustrated in Figure 3. It begins by configuring the RF channel sampling based on the input signal’s envelope characteristics. The average level is converted to input power using the coupler and RF detector characteristics (Equation 1). Conditional checks determine the state of the LNA and digitally controlled attenuator. If the current state matches the circuit state, the configuration phase is skipped. Otherwise, the circuit is configured accordingly.
[Images: RF AGC Algorithm]
The simulation results of the RF AGC algorithm, shown in Figure 4, demonstrate that when the RF input power changes from -95 dBm to +5 dBm, the RF output power varies from [-73 dBm to -8.2 dBm], reducing the input signal fluctuation from 100 dB to 64.8 dB.
[Image: RF AGC Simulation Results]
On the basis of RF adjustment, the IF feedback AGC performs continuous precision control of the gain. The algorithm is shown in Figure 5. The initial VGA control voltage (VGint) is set, followed by determining the IF channel sampling based on the input signal’s envelope. The mean VIFDET is calculated, and under non-constant envelope conditions, there is a T1-second interval between samples. The VGA gain and control voltage follow a linear relationship under normal operation (Equation 2).
[Images: IF AGC Algorithm]
According to the VGA device characteristics, k = 50 and b = -5. The IF detector output voltage (VIFDET) and IF output power (PIFOUT) conform to a linear relationship (Equation 3), where k1 = 0.05 and b1 = 2.575.
In the IF AGC loop, if PIFIN is the IF input power and PIFOUT is the IF output power, the loop target is to maintain PIFOUT at a target power (PAIM) when PMIN < PIFIN < PMAX. Assuming the current output power is PNOW, the VGA control voltage is VG1, and the IF detector output voltage is VIFDET, after one adjustment, the VGA control voltage becomes VG2, achieving PAIM. Using Equations 2, 3, and the control goal, Equation 4 is derived, where NSTAGE = 2 and PAIM = -19 dBm.
[Image: IF AGC Control Algorithm]
Based on the control target and the relationships in Equation 4, the judgment condition and control voltage calculation for Figure 5 are provided. VGint is the current VGA control voltage, Max[] represents the maximum value operation, and Min[] represents the minimum value operation. Since the detector only follows Equation 3 within a certain range, a reliable detection voltage interval [0.375 V, 2.75 V] is defined. Within this range, VIFDET is considered to represent the true output power. If VIFDET < 0.375 V, the VGA gain is increased to bring VIFDET into the confidence interval. If VIFDET > 2.75 V, the VGA gain is reduced.
[Image: IF AGC Simulation Results]
3. Algorithm Implementation and Testing
The hybrid AGC algorithm is implemented on the Xilinx Spartan 3E Series FPGA, as described in Section 2. Key components include the ADC, RF switch, digitally controlled attenuator, and DAC. The RF and IF sections share a 10-bit, 4-channel ADC (ADS7954). The RF switch is controlled by the FPGA’s high/low level output. The digitally controlled attenuator is a 6-bit, 0.5 dB step RFSA2644 chip. The IF VGA control voltage is provided by a 12-bit DAC. All ADC channel switching, attenuation values, and DAC output voltages are controlled via the SPI bus.
To facilitate digital processing, the sampling times N1, N2, N3, and N4 in the proposed algorithm are powers of two.
The functional simulation results of Modelsim under different input conditions are shown in Figure 7. When the input is a constant envelope signal (Figure 7a), the RF channel is first configured, with four RF samples taken. After calculations, the digital attenuator is configured. Due to high input power, the LNA is always off, and the VGA gain is preset. Then the ADC switches to the IF channel for 16 consecutive samples, and the DAC outputs the appropriate VGA control voltage. A single AGC cycle for a constant envelope signal takes 41.73 μs.
[Image: Constant Envelope AGC Simulation]
When the input is a non-constant envelope signal (Figure 7b), the RF AGC sample count increases to 64, while the IF AGC remains at 16 samples. A 6.68 μs interval is added between samples, resulting in a total control time of 230.53 μs. The time-domain input and output waveforms measured by the oscilloscope are shown in Figure 8. Channel 1 is the input sinusoidal envelope signal with a period of 128 μs, and Channel 2 is the IF output signal. It can be observed that the output signal envelope remains intact, and the average power is constant.
[Image: Non-Constant Envelope AGC Simulation]
The key parameter curves of the hybrid AGC loop versus RF input power are shown in Figure 9 under constant envelope input conditions. The curve fitted according to Equation 1 in Figure 9a aligns well with the measured data. The VGA control voltage in Figure 9b exhibits three-step transitions, consistent with the four conditional judgments in the RF AGC algorithm. Figures 9c and 9d show that the designed AGC system maintains a constant output power of -19 dBm over an input dynamic range of -100 dBm to +10 dBm. The dynamic range comparison of recent AGC systems is shown in Figure 10 [5–16]. The results indicate that the dynamic range achieved in this paper is competitive.
[Images: AGC Parameter Curves]
4. Conclusion
This paper proposes a hybrid high dynamic range AGC algorithm based on the receiver’s hardware architecture, combining the advantages of feedforward and feedback AGC. Implemented on an FPGA platform, the algorithm uses key components such as an RF switch, digitally controlled attenuator, detector, and VGA to achieve an input dynamic range of 110 dB, a sensitivity of -100 dBm, and an output power of -19 dBm. Under both constant and non-constant envelope inputs, the algorithm execution times are 41.73 μs and 230.53 μs, respectively, with the signal envelope preserved. The results show that the proposed AGC algorithm delivers excellent dynamic range performance.
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