Abstract: A hybrid high dynamic range AGC algorithm is proposed for receiver applications. The algorithm integrates RF feedforward and IF feedback mechanisms, implemented using a field programmable gate array (FPGA). Under the control of this algorithm, with key components such as an RF switch, digitally controlled attenuator, detector, and variable gain amplifier (VGA), an automatic gain control loop is realized. This system achieves an input dynamic range of 110 dB, a sensitivity of -100 dBm, and an output power of -19 dBm.
0. Preface
Due to factors like multipath fading, the signal power at the antenna of a receiver can fluctuate by more than 60 dB [1]. The fixed dynamic range of the IF ADC makes it difficult to accurately sample such large variations in signal strength. To ensure correct demodulation and decoding in the baseband, the receiver must adjust its gain automatically based on the input signal strength, maintaining a relatively constant output for subsequent stages. This function is achieved through the Automatic Gain Control (AGC) loop.
Common AGC loops are categorized into three types: feedforward AGC, feedback AGC, and hybrid AGC [2-4]. Feedforward AGC uses open-loop control, where the input signal power is detected and used to adjust gain. Feedback AGC operates in a closed-loop, comparing the output power with a reference value to determine the gain adjustment. Research in [3] indicates that feedforward AGC has a faster response and simpler implementation, making it widely used. However, it is sensitive to circuit parameter changes, leading to potential misalignment. Feedback AGC offers more stable control but requires careful tuning of loop parameters, which complicates design. Hybrid AGC combines both approaches, offering the benefits of both.
1. Hybrid AGC Loop
The hybrid AGC loop integrates an RF feedforward AGC circuit and an IF feedback AGC circuit within the receiver. As shown in Figure 1, the received signal is coupled into the RF detector. The detector's output voltage is converted into a digital signal via an ADC, then processed by the FPGA through a single-pole double-throw switch and a digitally controlled attenuator to adjust the RF gain. The Low Noise Amplifier (LNA) provides 22 dB of gain, while the attenuation network reduces it by 10 dB. The RF signal is mixed with a local oscillator to produce the intermediate frequency (IF) input signal, IFIN. This signal is amplified by two stages of VGA before being fed back to the IF detector. The detector’s output voltage is digitized and processed by the FPGA, which controls the VGA gain via a DAC. The IF output signal (IFOUT) and the VGA control voltage (VG) are key variables in this process.
2. AGC Algorithm
Before introducing the AGC algorithm, the loop design specifications are outlined. The designed AGC must handle two different types of input signals. For constant envelope signals, the AGC should respond in less than 50 μs, with an input dynamic range of at least -95 dBm to 5 dBm and an output power of -19 dBm. For non-constant envelope signals, the envelope must remain undistorted.
Based on these specifications, the overall algorithm in Figure 2 is designed. The system determines the envelope characteristics of the input signal externally. Upon startup, the system checks if the input is a constant envelope signal. If so, it executes the fast AGC algorithm; otherwise, it runs the slow AGC algorithm. The process alternates between RF and IF AGC, repeating after a set time interval.
The RF feedforward AGC algorithm, as shown in Figure 3, begins by configuring the ADC sampling for the RF channel, determining the number of samples based on the input signal's envelope. The average level is converted to input power using the coupler and RF detector characteristics (Equation 1). Conditional judgments are made on the detected power to determine the state of the LNA and the digitally controlled attenuator. If the current configuration matches the circuit state, the configuration phase is skipped. Otherwise, the circuit is reconfigured accordingly.
Simulation results of the RF AGC algorithm, shown in Figure 4, demonstrate that when the RF input power varies from -95 dBm to 5 dBm, the RF output power ranges from [-73 dBm, -8.2 dBm], reducing the input signal fluctuation from 100 dB to 64.8 dB.
On top of RF adjustments, the IF feedback AGC performs continuous precision gain control. The algorithm, illustrated in Figure 5, starts by assigning an initial value to the VGA control voltage (VGint). The number of IF channel samples is determined based on the input signal's envelope. The mean VIFDET is calculated, and under non-constant envelope conditions, there is a T1-second interval between samples. The VGA gain and control voltage VG follow a linear relationship (Equation 2), where gain is in dB and voltage is in volts.
Using the VGA device characteristics, k = 50 and b = -5. The IF detector output voltage (VIFDET) and IF output power (PIFOUT) conform to a linear relationship (Equation 3), with voltage in volts and power in dBm. From the detector and coupler characteristics, k1 = 0.05 and b1 = 2.575.
In the IF AGC loop, the target is to maintain PIFOUT at a target power (PAIM) when PMIN < PIFIN < PMAX. Assuming the current output power is PNOW and the VGA control voltage is VG1, after one adjustment, the control voltage becomes VG2, and the output power reaches PAIM. Using Equations 2, 3, and the control target, Equation 4 provides the control algorithm, where NSTAGE = 2 and PAIM = -19 dBm.
Based on the control target and the relationship in Equation 4, the judgment condition and control voltage calculation for Figure 5 are defined. VGint is the current VGA control voltage, Max[] represents the maximum operation, and Min[] represents the minimum. Since the detector only follows Equation 3 within a certain range, a reliable detection voltage interval [0.375 V, 2.75 V] is established. Within this range, VIFDET reflects the true output power. If VIFDET < 0.375 V, the output power is considered low, and the VGA gain is increased to bring VIFDET into the confidence interval. If VIFDET > 2.75 V, the VGA gain is reduced, and the process is repeated.
The simulation results of the IF AGC algorithm, shown in Figure 6, indicate that when the IF input power ranges from -100 dBm to -10 dBm, the VGA control voltage VG adjusts with the input power, keeping the output power at -19 dBm. VIFDET and PIFOUT change synchronously, achieving the goal of loop power control.
3. Algorithm Implementation and Testing
As described in Section 2, the hybrid AGC algorithm is implemented on the Xilinx Spartan 3E Series FPGA. Key components include the ADC, RF switch, digitally controlled attenuator, and DAC. The RF and IF sections share a 10-bit, 4-channel ADC (ADS7954). The single-pole double-throw switch is controlled by the FPGA’s high/low-level output. The digitally controlled attenuator is a 6-bit, 0.5 dB step RFSA2644 chip. The IF VGA control voltage is provided by a 12-bit DAC. All ADC channel switching, attenuation values, and DAC output voltages are controlled via an SPI bus.
To facilitate digital processing, the sampling times N1, N2, N3, and N4 in the algorithm are chosen as integer powers of two.
Functional simulation results from Modelsim under various input excitation conditions are shown in Figure 7. When the input is a constant envelope signal (Figure 7a), the RF channel is first configured, with four RF channel samples taken. After calculation, the digitally controlled attenuator is configured. Due to high input power, the LNA remains off, and the VGA gain is preset. The ADC is then switched to the IF channel for 16 consecutive samples, followed by DAC configuration to output the appropriate VGA control voltage. A single AGC process for a constant envelope input takes 41.73 μs.
When the input is a non-constant envelope signal (Figure 7b), the RF AGC sample count increases to 64, while the IF AGC still samples 16 times, with a 6.68 μs interval between samples. The total control time is 230.53 μs. Time-domain input and output waveforms measured by an oscilloscope are shown in Figure 8. Channel 1 is the input sinusoidal envelope signal with a period of 128 μs, and Channel 2 is the IF output signal. It is observed that the output signal envelope remains intact, with a consistent average power.
The curve of key parameters in the hybrid AGC loop versus RF input power, under a constant envelope input, is shown in Figure 9. The curve fitted according to Equation 1 in Figure 9(a) aligns well with the measured data. The VGA control voltage in Figure 9(b) exhibits three distinct transitions, corresponding to the four conditional judgments in the RF AGC algorithm. Figures 9(c) and 9(d) show that the designed AGC system maintains a constant output of -19 dBm over an input power range of -100 dBm to 10 dBm, achieving a dynamic range of 110 dB. A comparison of the dynamic range of the proposed AGC system with recent systems is shown in Figure 10 [5-16]. The results indicate that the dynamic range achieved in this paper is competitive.
4. Conclusion
This paper proposes a hybrid high dynamic range AGC algorithm tailored for receiver hardware, combining the features of feedforward and feedback AGC. Implemented on an FPGA platform, the algorithm utilizes RF switches, digitally controlled attenuators, detectors, and VGAs to achieve an automatic gain control loop with an input dynamic range of 110 dB, sensitivity of -100 dBm, and output power of -19 dBm. Under both constant and non-constant envelope inputs, the algorithm execution times are 41.73 μs and 230.53 μs, respectively, with the signal envelope preserved. The results demonstrate that the proposed AGC algorithm achieves excellent dynamic range performance.
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