Train voice recording device based on MPEG-2 algorithm

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Abstract : This paper introduces the system architecture, characteristics and hardware and software implementation methods of a new type of train voice recording equipment. Using DSP technology to process, compress and record the voice signal, the locomotive voice linkage control and the current state information of the train are recorded, and then the flight attendant's working terms are standardized and the monitoring device is analyzed to analyze the driving fault.
Keywords : A/D conversion; speech data coding; cyclic redundancy check

Foreword The train operation monitoring and recording device plays a huge role in the safe transportation of the railway, but the lack of voice recording function. In order to solve this problem, according to the technical requirements of the Ministry of Railways, this paper researched and developed a new type of train voice recording equipment. The equipment is mainly used for recording the flight attendant joint control of the flight attendants, and can cooperate with the monitoring device to analyze the traffic accidents, and provide new technical means for the scientific management of the maintenance department and the transportation department. In view of the technical specifications and standards of common equipment, for the digitization of speech, the sampling frequency of 16KHz and the quantization precision of 16 bits are used for sampling. In coding, MPEG-2 compression coding is adopted.

Hardware system composition
The voice recording device is shown in FIG. 1 , and the whole system is composed of an ADC, a DSP, a CPLD controller, a Flash mass storage device, and an LCD display screen.

In this system, the ADC is used to complete the signal conversion. The data format is optional between 16, 18 and 20 bits. The DSP is the core digital processor of the system. It is powerful and completes the compression coding of digital signals. CPLD is used for data. Control of the transfer and initialization detection settings for devices such as ADC, Flash, and LCD display. Flash is used to store data. The LCD display is used to display the current system status, such as run wait and data processing. After the system is powered on, if there is a voice signal, the ADC is input, and a series of digital signals are sent to the DSP for data compression coding. The compressed coded data is stored in the Flash by the CPLD, and the whole system works in a pipeline manner, and the data is collected. , compression coding and storage are performed simultaneously.

A/D converter UDA1341TS
The UDA1341TS is a monolithic stereo A/D, D/A converter manufactured by Philips. It operates at 3.0V and has a signal-to-noise ratio of 97dB. It has dual input functions and sampling frequencies of 16, 32 and 44.1KHz. Optional.

The UDA1341TS and DSP form a speech signal acquisition system, which mainly involves a bit sampling clock (BCK), a word synchronous clock (WS), a sampled data output (DATAO), and a system clock input (SYSCLK), which are required for timing. In the system, DATAO is used as an output pin and connected to the BDR0 pin of the DSP; BCK, WS, and SYSCLK are used as input pins, and the timing is supplied by the DSP. The system clock of UDA1341TS can only be 256Fs, 384Fs, 512Fs. The system clock can be selected by programming the SC0 bit and SC1 bit of the status register. Here Fs is the sampling frequency of the speech signal. When sampling data, WS is used to indicate valid data for the DATAO output of the UDA1341TS. When the system samples the VINL (left channel) port, the rising edge of WS indicates the start of a frame of data, the falling edge indicates the end of a frame of data; when the system samples the VINR (right channel) port, WS The falling edge indicates the start of a frame of data, and the rising edge indicates the end of a frame of data.


Figure 1 Overall structure of the system

The UDA1341TS provides an L3 port that uses the CPLD controller to program the L3's L3DATA, L3MODE, and L3CLOCK pins to set its internal registers. When the L3MODE pin is low, the register address information is input through the L3DATA pin; when the L3MODE pin is high, the data information about the register setting is input through the L3DATA pin (such as setting the chip system clock frequency, data input format, Chip working mode, etc.). The UDA1341TS is connected to the McBSP (multi-channel buffer synchronous serial port) of the DSP, and various synchronization signals are generated by the DSP, thus ensuring the normal reception of new data and the normal processing of the received data. The hardware connection between UDA1341TS and DSP is shown in Figure 2.

Speech encoder TMS320VC5402
The compression of digital voice signals requires a large amount of digital signal processing. Generally, the single-chip microcomputer cannot be completed. Therefore, the system uses TI's DSP chip TMS320VC5402 (hereinafter referred to as C5402) to compress the voice signal.

The C5402 communicates with the voice sample converter UDA1341TS via its McBSP. McBSP provides a full-duplex communication mechanism, as well as a dual-cache transmit register and a triple-buffer receive register, allowing continuous data stream transfer with data widths between 8, 12, 16, 20, 24, and 32 bits; The communication between McBSP and ADC is realized by BDR0 pin, and the control of communication process is realized by three pins such as BCLKR0, BCLKR1 and BFSR0.


Figure 2 UDA1341TS and DSP hardware connection diagram

CPLD Low Speed ​​Control DSP is not suitable for low speed control applications as a high speed arithmetic processor. The detection, initialization, control of the LCD, and storage control of the Flash for the UDA1341TS are low-speed controls. This system uses CPLD to complete these tasks. CPLD is Altera's EPM7128S, and the development simulation environment is Altera's MAX-PLUSII. Because the address lines A0, A1, and A2 of the DSP are to be used by some chips, a total of 6 address lines and I/O space selection signals of A3-A7 and A15 are selected to jointly generate the strobe signals of the chips in the system. The control circuit in the CPLD is responsible for generating various read and write signals, such as the read signal MEM_RD of the flash and the write signal MEM_WR.

In this system, the C5402 generates a lot of control signals (such as the selection signal of the Flash program page PPG2-PPGO, etc.), and also monitors and reads the external status. Because the C5402 has only two general-purpose I/O pins, it uses CPLDs to extend its I/O ports. The CPLD internally outputs data through an 8-bit DFF flip-flop. In addition, the 8-bit input state is placed on the lower 8 bits of the C5402 data bus through eight tri-state gates. The C5402 has 4 interrupt inputs. The interrupt selection module of the CPLD can select 4 out of up to 8 external interrupt signals as the interrupt input of the C5402, which improves the flexibility of the system.


Figure 3 system main program

Software design software design mainly includes ADC program design, compression coding of voice data and so on.

ADC programming ADC sampling with 16KHz sampling frequency and 16-bit quantization precision. The sampled bit synchronization signal, frame synchronization signal and data bit clock signal are all provided by DSP, so the programming of McBSP related registers, such as pin control register. (PCR) programming, serial controller (SPCR1, SPCR2) programming, receive control registers (RCR1x, RCR2x) and transmit control registers (XCR1, XCR2) programming will affect the final effect of the voice signal, so the user must See the relevant materials for details.


Figure 4 Intra coding process


Speech data coding This paper adopts the general MPEG-2 speech compression coding algorithm, which is frame data structure coding. The sample value of one frame is 576, calculated by the 16KHz sampling frequency of UDA1341TS, and the coding requirement of one frame data is completed within 72ms. . The instruction cycle of the C5402 is 10 ns. In the case of satisfying the algorithm requirements, it takes about 10 ms to perform dual-channel real-time encoding, so the C5402 can complete the real-time encoding of the algorithm. It mainly includes the following aspects: operation of filter bank; operation of psychoacoustic model; quantization coding; frame data formatting.

The role of the filter bank is to complete the mapping of the signal from the time domain to the frequency domain. The psychoacoustic model is calculated by using the 1024-point FFT to perform spectrum analysis on the input speech signal, and then combining the results of time-frequency mapping to calculate the masking characteristics of each sub-band. The quantization coding is a process of performing linear quantization coding on each sub-band data by calculating the bit allocation information required for each sub-band coding by the masking characteristics of each sub-band and the output bit rate. The subsequent work of the program is to format the data according to the MPEG-2 standard. The purpose is to enable the data to be correctly decoded after encoding. The main program of the system is shown in Figure 3.

Intra-frame coding is a DSP that compresses and encodes a digital voice signal transmitted from an ADC according to the MPEG-2 standard. The flow is shown in FIG.

Conclusion
After the system is powered on, after many experiments, the operation is stable. At present, the equipment has been on-site commissioning and operation, and part of the loading operation has begun, which meets the actual requirements of train voice recording.

references:
1 Philips Semiconductors. UDA1341TS Product specification [Z].Netherlands: Philips Semicon ductors, 2002

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