Atheros on Ralink, see RF circuit design for WiFi products

This article was written with my years of work experience and practice. This is a highly targeted technical article. In this article, I have only analyzed the general RF circuit design of Wi-Fi products, and mainly analyzed the solutions of Atheros and Ralink. The solutions of other vendors have not been studied. I hope to be able to help everyone in the design work.

I. Preface

This is a technical article that is not very targeted. In this article, I studied and discussed the RF circuit design in Wi-Fi products, including various components, such as wireless transceivers, power amplifiers, and low-noise amplifiers. If you discuss a part of this article, you can Write a very thick book.

This article is general. Although this article mainly analyzes Atheros and Ralink's solutions, the solutions of these two vendors are very representative and have a high market share. Therefore, most Wi-Fi products must be consistent or A similar architecture. People who frequently browse related websites must know that wireless routers that are popular in the Chinese market, wireless APs are many of these two solutions.

This article has some practicality. This article is based on more than 20 reference design circuits of our company, fully absorbs the essence of the reference design, and extracts its generality. At the same time, this article also focuses on the analysis of the actual circuit structure and the selection of devices should pay attention to The problem has not been studied in depth, so this article has certain practicality.

This article was written by me in my spare time (also I can kill time in this way). If this article can bring a little help to everyone's work, it will be my happiest thing.

Chapter 1. RF Design Block Diagram

When you are technical and explain the principle of a design, you will start with a block diagram. I am no exception. Let me show you the general RF design block diagram of Wi-Fi products.

Figure 1-1 General RF design block diagram of Wi-Fi products

As shown in Figure 1-1, the RF part of a typical Wi-Fi product consists of five parts (this is my personal opinion, different engineers may have different ideas), and the blue dotted line is uniformly regarded as power. Amplifier section. Radio Transceiver (Radio Transceiver) is generally one of the core components of a design. In addition to its close relationship with RF circuits, it is generally related to CPU. Here, we only pay attention to some of its contents related to RF circuits. When transmitting a signal, the transceiver itself directly outputs a weak RF signal of a small power, and sends it to a power amplifier (PA) for power amplification, and then radiates through an antenna (Antenna) through a Transmit/Receive Switch. space. When receiving the signal, the antenna senses the electromagnetic signal in the space, and then sends it to the Low Noise Amplifier (LNA) for amplification by the switch, so that the amplified signal can be directly sent to the transceiver for processing. demodulation.

In the following explanations, I will expand the various parts in Figure 1-1 one by one, and expose each one to everyone's eyes. I will also explain the design of each part in detail. I believe that after reading this document carefully and carefully, It is possible to have a clearer understanding of the various components of the RF.

Chapter 2. Wireless Transceiver

I put the wireless transceiver (referred to as the transceiver in the following section of this chapter) in the first module, the main reason is that it is generally one of the core components of a design, and sometimes it may be integrated on the CPU. It will be the most important chip in a design. At the same time, of course, the importance of the transceiver determines its peripheral circuitry must be complex, and in fact it is. Moreover, if there is no reference design, completely designed by us, this chip is also the first priority we should consider, this chip fundamentally determines the wireless performance of the entire design. In this way, the design of this part will be more difficult to explain, but I still want to explain it first.

Transceivers usually have a lot of pins. In Figure 2-1, I only give the pins that I will pay attention to when designing the RF circuit. I can see that there are several power pins, digital ground, analog ground, RF output, power amplifier gain control, power detection, temperature detection, RF input, low noise amplifier gain control, transmit and receive switching, etc. In the following content, I will explain these pin sub-modules one by one.

Figure 2-1 General wireless transceiver chip (related to RF circuit design)

2.1. Technical parameters of the wireless transceiver chip

Different designs, transceivers will generally be very different, we will not think about replacing it most of the time. Generally, we choose the transceiver, which will be directly in accordance with the reference design. However, I still talk about some parameters (RF circuit related parameters) that should be concerned when selecting a wireless transceiver from the perspective of a developer.

2.1.1. Protocol, frequency, path and transmission rate

In the transceiver's Datasheet, generally in the first few paragraphs, it is pointed out which protocols are supported by the chip, on what frequency, and several paths (that is, several shots). Our current main product design is Is supporting 802.11n. The importance of these three parameters must not be said by me, and everyone should understand it. Their parameters determine the function of the final product.

A typical description such as: The Atheros AR9220 is a highly integrated single-chip soluTIon for 2.4GHz and 5GHz 802.11n-ready wireless local area network (WLANs) that enables high-performance 2&TImes;2 MIMO configuraTIons for wireless staTIons applications demanding robust link Quality and maximum throughput and range.

From this description, we can know that the AR9220 supports the 802.11n draft (generally compatible with 802.11b/g). At the same time, the AR9220 also supports dual-band, 2.4GHz and 5GHz, so we can know that it also supports 802.11a. 2×2 MIMO Description The AR9220 is a second-in-two-out (2T2R).

Transmission rates are closely related to protocols and pathways, and interested colleagues can access relevant information.

From the AR9220's Datasheet, we can know that the 20MHz bandwidth, the maximum transmission rate can reach 130Mbps, the highest transmission rate can reach 300Mbps when the bandwidth is 40MHz.

2.1.2. Modulation method

The modulation mode and the transmission rate are closely related, and different transmission rates correspond to a different modulation mode. The modulation modes supported by the chip are generally given in the characterization of the Datasheet. For example, the AR9220 supports modulation methods such as BPSK, QPSK, 16QAM, 64QAM, DBPSK, DQPSK, and CCK.

2.1.3. Clock frequency

The clock frequency, the clock frequency includes two kinds, the frequency of the external crystal of the transceiver and the operating frequency after the internal multiplication. This parameter should also be our concern.

2.1.4. Output power

There is a phenomenon I have been confused about, why is it not given its transmit power in the transceiver's Datasheet? This parameter is very important for our RF engineers. Because this parameter determines the design of the subsequent power amplifier circuit, we must ensure that the output power of the transceiver is enough to drive the power amplifier, so that we can design a reasonable and effective amplifier.

2.1.5. Receive sensitivity

As with the output power, the transceiver receiving sensitivity parameter will not be given in the Datasheet. In the actual design process, with this parameter, we can reasonably design the amplification factor of the low noise amplifier to ensure low noise. The output of the amplifier can be effectively accepted by the transceiver.

2.1.6. RF interface

This parameter relates to the structure of our subsequent RF circuits. In general, the transceiver should have RF input pins including: RF output pin, power amplifier gain control pin, power amplifier output power detection input pin, low noise amplifier gain control pin, switch transceiver control pin In general, Ralink's solution will also have a PA temperature detection pin.

2.1.7. Supply voltage and power consumption

From a global perspective, the supply voltage and power consumption are also the technical parameters we have to pay attention to. These two parameters are related to the design of the power supply circuit and the design of the heat dissipation.

2.2. Processing of differential RF signals

2.2.1. The pins of the transceiver itself

For RF signals, in order to enhance the anti-interference ability of the transceiver, differential signal processing is generally adopted, that is, the transceiver transmits the signal in a differential form, and the external circuit must also provide a differential RF signal for the transceiver. enter. As shown in Figure 2-2, the four pins in the red box are the input of the differential RF signal of the transceiver, and the output pin is also the most important RF signal pin.

Figure 2-2 RF input and output pins of the transceiver

It must be pointed out here that Atheros' transceivers generally do differential processing of inputs and outputs at the same time. However, Ralink generally requires externally input signals to be differential, while the RF signals output by itself are not differential. Figure 2-3 and Figure 2-4 show the main RF signal pins for RT3052 (Ralink) and AR9220 (Atheros), respectively. It is not difficult to find that Atheros's design is more delicate than Ralink. It is not just a transceiver chip. In the design of subsequent circuits, Atheros will also consider the problems considered. I think this is what we should have as a developer. a spirit.

Figure 2-3 Main RF signal pins of the RT3052

Figure 2-4 Main RF signal pins of the AR9220

2.2.2. Differential signals transmitted by the transceiver

The differential signals sent by the transceiver, we have to find a way to combine them into one. Why do you want to do this, the signal sent by the transceiver is to be given to the power amplifier circuit, and the power amplifier circuit is to process the single-ended signal.

Balancers are often used to deal with differential signal problems. In addition, we know that both inductors and capacitors can change the phase of the signal. From differential signals to single-ended signals, the basic method is to use inductors and capacitors to make two different In this way, the two signals passing through the processing circuit are 180° out of phase, so that the differential signals with the original phase difference of 180° can be in phase to obtain a single-ended signal. Conversely, a single-ended signal is passed through two different paths, resulting in a differential signal.

Let's take a look at the circuit form of the two methods separately.

Method one, use a balancer. The differential signal with a phase difference of 180° is passed through a balancer (Balun, commonly known as balun), and a single-ended RF signal can be obtained. As shown in Figure 2-5, F1 in the figure is a balancer. The differential signals RFOUT_P and RFOUT_N get the single-ended signal RF_OUT through F1.

Figure 2-5 Typical Balance Circuit

Method two, using discrete components. A typical processing circuit using discrete components is shown in Figure 2-6.

Figure 2-6 Typical discrete component processing circuit

2.2.3. Parameters and selection of the balancer

In Atheros's solution, the balancer is often used a lot, I will give the main parameters of the balancer and a brief selection guide. As mentioned earlier, in our Wi-Fi products, the balancer is often used to process differential signals. The main parameters are as follows:

Unbalanced impedance

Balanced impedance

working frequency

Unbalanced port return loss

Phase change

Insertion loss

For example, the typical parameters of the commonly used balancer HHM1711D1 are shown in Figure 2-7. In this way, we can choose the right balancer according to our needs.

Figure 2-7 Typical parameters of the HHM1711D1

2.2.4. Differential signals received by the transceiver

The signal received by the transceiver comes from the low-noise amplifier at the front end. Like the power amplifier, the low-noise amplifier processes the single-ended RF signal, so we must convert the signal output from the low-noise amplifier. Similarly, there are two ways to handle the output signal of a low noise amplifier: using a balancer and using discrete components. Some of Atheros's solutions use balancers; Ralink's solution has not been used yet.

In fact, everyone must have thought that the transceiver receiving signal and the transceiver sending signal are almost the opposite process, so the structure of the circuit is almost the opposite. That's right, I saw the actual circuit diagram below. Let me introduce the scheme of using the balancer. In a practical case, the balancer circuit shown in Figure 2-8 is used. The single-ended signal RF_IN passes through the balancer F5 to obtain differential RF signals RFIN_P and RFIN_N.

Figure 2-8 Balancer circuit used in a case

Let's take a look at the methods implemented with discrete components. Figure 2-9 shows the usual way of using Ralink. Figure 2-10 shows the common processing methods of Atheros. It can be seen that the two design methods are similar.

Figure 2-9 Ralink commonly used discrete component signal processing

Figure 2-10 Atheros commonly used discrete component signal processing

2.3. Transceiver Power Pins

Transceivers generally have a large number of power pins, which can be roughly divided into several categories. As can be seen from Figure 2-2, there will be main power pins, core voltage power pins, IO power pins, phase-locked loops. (Phase Lock Loop, PLL) power pin, etc.

In the design of RF circuits, we generally pay more attention to analog power supplies. For the RF circuit power supply, if I choose between a linear regulated power supply (LDO) and a switching power supply (DC/DC), then I will not hesitate to choose a linear power supply.

why? And the switching power supply has hatred? There is indeed hatred!

Until now, I have clearly remembered the experience in the university. Once I designed a campus broadcasting equipment for a university, considering the large output power of campus broadcasting, the requirements for power supply were more demanding. I went to the technology market and found a well-made switching power supply. At that time, I was deceived by the gorgeous appearance of this guy and bought it without hesitation. However, when I was completely designed, I turned on the power, and the sound from the radio was not a pleasant music sound, but a very disgusting "squeaky" sound, a huge hum. In order to solve this problem, I almost racked my brains and redesigned the parts that might cause problems, but the problem remained unresolved. Later, I suddenly realized: "Is it a problem with switching power supplies?" Just have a car radio power supply (high-power linear regulated power supply). When I connect this power supply, wow, the whole world is quiet! Switching power supply not only lost some money, but also wasted a lot of time. Since then, my design has never used switching power.

For the power supply pins of the transceiver, the usual processing method is to place a 0.1uF capacitor at the pin of each power supply. Next to the power-consuming pins, a larger capacity capacitor, 1-10uF or Bigger. In general, the analog power supply and digital power supply of the transceiver should be separated by inductors or magnetic beads, and the capacitor with a relatively large capacity must be placed behind the inductor or the magnetic beads. If conditions permit, it is best to place the electrolytic capacitor. It will greatly improve the performance of the power supply. At the same time, several small-capacity ceramic capacitors can be connected in parallel to filter out the AC components of different frequencies.

2.4. Transceiver complete peripheral circuit design

Recall that in the previous description, we explained how to select the transceiver, the differential signal processing related to the transceiver, and the power supply of the transceiver. These three aspects basically cover the content of the transceiver RF circuit design. In other words, to understand these three parts, basically complete the design of this part.

Presumably everyone should be clear about the structure of the three parts, well, let us try, put some devices on the periphery of the chip in Figure 2-2, and then connect several lines to complete the wireless transceiver and its peripheral circuit design. Here, we process the differential signal output from the transceiver with a balancer to obtain a single-ended signal RFOUT. The received signal RFIN from the low-noise amplifier is processed by discrete components to obtain the differential signals RFIN_P, RFIN_N. In this way, the schematic shown in Figure 2-11 is obtained.

Figure 2-11 Completely designed wireless transceiver peripheral circuit

Chapter 3. Power Amplifiers

Power amplifier, Power Amplifier, commonly known as PA, is mainly used to power-amplify the RF signal sent by the radio transceiver (Radio Transceiver) to ensure that there is enough output power to meet the design requirements. The design of the power amplifier is a very professional topic, and there are many people. Many senior RF engineers have done in-depth research in this area. I will only discuss the common design methods of our Wi-Fi products here.

In our products, the composition of the power amplifier is nothing more than a chip with several peripheral devices, but in the case of high power, almost no one uses the integrated circuit for power amplification, which is generally designed with discrete components. , transistor or FET. In all of our current designs, power amplifiers are implemented using integrated circuits. As shown in Figure 3-1, it is a block diagram of the design of a typical power amplifier.

Figure 3-1 Block diagram of the power amplifier

The design of the power amplifier will consider many parameters, but it is mainly divided into three categories: gain, noise, and nonlinearity. The gain is related to the final output power, which is related to signal quality.

Here I will divide the power amplifier (referred to as the power amplifier in the following contents of this chapter) into the following sections: the selection of the power amplifier chip, the power supply of the power amplifier chip, the input loop, the output loop, the power detection, the gain control, and the temperature detection.

3.1.1. Pins of the power amplifier chip

The power amplifier chip belongs to the category of microwave power devices. Figure 3-2 shows the schematic symbol of a typical power amplifier chip, including the following pins:

VCC main power supply pin

VC1 primary power amplification power supply pin

VC2 secondary power amplification power supply pin

RFIN RF signal input pin

RFOUT RF signal output pin

One of the GAIN_1 gain control pins

GAIN_2 Gain Control Pin 2

POWER_DETECT built-in power detection output pin

Figure 3-2 Typical power amplifier chip

It is worth noting that GAIN_1 and GAIN_2 are control signals from the Transceiver and are DC voltage. POWER_DETECT is the transmit power detection value of the output of the power amplifier chip, and is also the DC voltage. RFIN and RFOUT are the most important RF signal pins. .

3.1.2. Major manufacturers of power amplifier chips

Among the products on the market, the suppliers of power amplifier chips are basically these four: SiGe, SST, Microsemi, Richwave, Table 3-1, Table 3-2 shows the power amplifier chips used in several practical projects. model.

Table 3-1 Amplifier chips used in the design of Atheros

Table 3-2 Power amplifier chip used in Ralink design

From the above table, we can easily find out that Atheros likes Microsemi's chip, and Ralink prefers Richwave and SST. In the BCM4323 project, the power amplifier chip used is SiGe. In the current design of AP96, it is also used. SiGe's Frontend Module.

3.1.3. Main parameters of the power amplifier chip

The choice of power amplifier chip is a complicated process. In the actual selection process, we generally consider the following parameters:

working frequency

Small signal gain

Maximum linear output power

1dB compression point output power

Error vector magnitude (EVM)

Adjacent channel power ratio (ACPR)

Noise Figure

Whether built-in power detection function

Whether built-in gain control function

Supply voltage

Current consumed

The above parameters are not completely given in the Datasheet of each power amplifier chip, and some Datasheets can only give some parameters. The meaning of each parameter must be clear to everyone, I will not explain too much here. A typical power amplifier chip's Datasheet is as follows:

2.3-2.5GHz Operation

Single Positive Supply Voltage Vcc = 3.3V

Power Gain ~ 27dB

Quiescent Current ~ 90mA

EVM ~ -30dB at Pout = +19dBm

Total Current ~ 150mA for Pout = +19dBm

Pout ~ +26dBm for 11g OFDM Mask Compliance

Total Current ~220mA for Pout = +23dBm 1 Mbps DSSS

On-Chip Input Match

Simple Output Match

Robust RF Input Tolerance > +5dBm

Small & Low-Cost 3x3x0.9mm3 MLP Package

Cost Reduction over LX5510, LX5510B

From the above description, we learned that the power amplifier chip operates at 2.3-2.5 GHz and operates from a single 3.3V supply. The quiescent operating current is 90 mA. At 19 dBm power output, the EVM value is -30 dB.

The performance of the power amplifier chip is very important, of course, we will choose the cheapest when it meets the performance.

3.2. Power supply for the power amplifier chip

The general power amplifier chip shown in Figure 3-2 has three power pins, VCC, VC1, and VC2. VCC is the main power supply, VC1 is the first-stage amplified power supply inside the chip, and VC2 is the second-stage amplification inside the chip. Power supply. There is a very important issue here. VC1 and VC2 are not simple power supply pins. These two pins are usually not connected directly to the power supply. Usually, an inductor (or resistor) is connected in series and connected to the power supply. Why? What? This is because this is the pin that powers the power transistors (or FETs) inside the chip. Usually in a power amplifier circuit composed of separate components, we will see the collector at the transistor (or the drain of the FET). There are inductors on the strings, and the inductors are not easy to integrate into the chip. Therefore, it is necessary to place the inductor outside the chip. In this way, the power supply mode of the typical power amplifier chip is obtained, as shown in Figure 3-3.

Figure 3-3 Typical power amplifier chip power supply mode

In addition to the above mentioned inductance problems, another important point is that the analog signal processed by the power amplifier circuit is a formal analog circuit, so it is necessary to pay special attention to the power supply to be separated from the power supply of the digital circuit. Another extremely important issue is that, as shown in Figure 3-3, a filter capacitor combination needs to be placed at each power pin. For example, a combination of 100pF and 1000pF filter capacitors is placed at the VCC pin. The foot is a 10pF capacitor. The combination of filter capacitors is such that for the main power supply pin VCC, it is necessary to place as many capacitors as possible, and the capacity of these capacitors is preferably of different order of magnitude, for example, it can be combined: 10uF+1uF+0.1uF+ 1000pF+100pF+10pF, different capacity capacitors are used to filter out the disturbance of different frequency components. For the two pins VC1 and VC2, it should be noted that the capacity of the filter capacitor placed is small, usually 1-10pF.

3.3. Input loop

The input circuit of the power amplifier circuit generally includes two parts, one is a Band Pass Filter (BPF), and the other is a 匹配 type matching network. We are divided into two parts.

3.3.1. Bandpass filter

We know that there are 13 subcarriers in the 2.4 GHz band, the frequency is from 2.412 GHz to 2.437 GHz, and the frequency interval between adjacent channels is 500 MHz. It is easy to understand that the signal output from the transceiver (Transceiver) includes from 2.412. A frequency band from GHz to 2.437 GHz, therefore, in order to enable a useful signal to smoothly enter the power amplifier chip, useless messy signals are filtered out, and a band pass filter is generally placed on the input loop of the power amplifier chip.

There are three implementations of the bandpass filter. One is to use a dedicated bandpass filter that has been designed, which is used in many Ralink schemes; one is a bandpass filter composed of discrete components. Not a lot; the third method is almost proprietary to Atheros, which is a printed bandpass filter. The most prominent advantage of this filter is that it has no cost. The most prominent shortcoming is that it takes up a lot of space and requires clearance. Zone, this filter is used in AP51.

Designing a bandpass filter with discrete components requires a complicated calculation process and requires a strong mathematical foundation. We do not do much research here. Next we will discuss how to choose a bandpass filter that has been designed. There are not many parameters of the bandpass filter, mainly:

input resistance

Output impedance

Passband

Attenuation in the passband

Attenuation outside the passband

Normally, the finished bandpass filter, the input and output impedances are controlled to a nominal value of 50 ohms, and a chart is sufficient to reflect the characteristics of the passband. Figure 3-4 shows the relationship between the S21 parameters and frequency of our commonly used HMD845H. It is obvious that the pass band of the band pass filter is 2.4 GHz to 2.5 GHz, and the fading is fast for frequencies outside the pass band.

Figure 3-4 S21 parameters of the HMD845H

3.3.2. Type matching network

Matching, this matter is extremely important in RF design. Many times, we design or debug RF circuits, all of which are solving the matching problem. Always remember such a classic criterion: conjugate matching transmission power is the largest. The 匹配-type matching network is usually placed directly at the input end of the power amplifier chip, that is, at the pin of RFIN. Usually, the pin of the chip will not match 50 ohms, and we will not know the input characteristics of the pin. In this case, The need for a 匹配-type matching network can be imagined.

The 匹配-type matching network, as the name implies, looks like a letter Π, let's take a look at the actual 匹配-type matching network. Figure 3-5 shows a type of matching network commonly used by Ralink.

Figure 3-5 Ralink commonly used type matching network

3.3.3. Completely designed input loop

Above we discussed the two components of the input loop of the power amplifier circuit, the bandpass filter and the 匹配-type matching network. With these two parts, we can design a complete input loop. As shown in Figure 3-6, it is a complete design of the input circuit of the power amplifier circuit. The U9 in the figure is a finished bandpass filter, while the C108, C109 and L14 form a 匹配-type matching network.

Figure 3-6 Input circuit of a fully designed power amplifier circuit

3.4. Output loop

In the output loop, the most important component (and the only component in many designs) is the low-pass filter. At this point, someone might ask why the low-pass filter is used here instead of the input loop. Bandpass filter? The reason is very simple. The main problem to be solved by the low-pass filter here is due to the higher harmonics caused by the power amplifier, such as the second harmonic, the third harmonic or even higher harmonics. Of course, the low-pass filter still needs to be The problem solved is the matching problem. In fact, in the design of RF circuits, this problem of matching will always be with us.

The design of the filter requires very complicated calculations. I don't want to explore too much theoretical knowledge here, so I don't give a way to calculate it, just give the general form of low-pass filter. It should be noted here that Atheros's design generally uses three components, while Ralink generally uses five components. As shown in Figure 3-7, it is a commonly used filter form of Ralink. In the figure, C112, C111, C113, C110 and C114 form a low-pass filter, and the signal PA_OUT from the power amplifier chip passes through the filter to obtain the LPF_OUT signal and sends it to the subsequent circuit.

At this time, we can connect the output of the power amplifier chip to the low-pass filter, and get the complete output loop of the general RF power amplifier circuit, as shown in Figure 3-8.

Figure 3-8 Completely designed power amplifier output loop

3.5. Power detection

The power detection function can be found in many of our designs. This function allows the radio transceiver (Radio Transceiver) to monitor the output power of the amplifier circuit at all times, so that when the output power of the amplifier changes, the wireless transceiver can be adjusted. The output power of the amplifier or the gain of the power amplifier circuit stabilizes the output power of the power amplifier circuit at a fixed value.

The power detection circuit outputs a DC voltage value. After the voltage value is sent to the wireless transceiver, the wireless transceiver itself performs A/D conversion, and the output power of the power amplifier circuit can be known.

There are usually two methods for power detection. In the design of Ralink, the power detection function of the power amplifier chip is usually used. In the design of Atheros, in addition to the power detection function of the power amplifier chip itself, there is usually one Atheros. The unique design we will discuss in two parts.

3.5.1. On-chip power detection

As we have seen in Figure 3-2, the general power amplifier chip has a pin such as POWER_DETECT, which is used for power detection. The chip's built-in power detection feature simplifies circuit design, as shown in Figure 3-9.

Figure 3-9 Common circuit forms using built-in power detection

3.5.2. Power detection circuit on the periphery of the chip

Here we use a separate section to discuss the peripheral detection circuit. In fact, it is Atheros's solution, because this design is too personal, let us see it together. As shown in Figure 3-10, it is the power detection scheme commonly used by Atheros. The PC1 in the figure is a Printed Coupler. The output signal LPF_OUT from the power amplifier passes through the coupler, and the high-frequency alternating voltage is sensed at pins 2 and 3. This voltage increases with the output power. Increase L18, L19, D1, C217, R248 to form a conventional rectifier circuit, so that the DC voltage POWER_DETECT changes with the change of output power, the wireless transceiver can get this voltage value and make corresponding action.

One thing to note here is that the rectifier diode D1 must select a diode with a high operating frequency. For example, the SMS7630 in this design operates at 10 GHz.

Figure 3-10 Power detection scheme commonly used by Atheros

3.6. Gain control

The function of the gain control is to change the gain of the power amplifier circuit so that the output power can be changed. There are two ways to change the final output power of a power amplifier. One is to change the output power of the wireless transceiver, and the other is to change the gain of the power amplifier circuit. Here we mainly focus on the latter. Usually, there are two or more gain control pins of the power amplifier chip, which change the gain values ​​of the first stage amplification and the second stage amplification respectively. Figure 3-11 is a typical gain control principle diagram. The control signal PA_GAIN from the transceiver is controlled by the RC filter circuit consisting of R245 and C248 (filtering out the possible AC component from the transceiver) by two resistors acting on the two pins GAIN_1 and GAIN_2 of the power amplifier chip, thereby controlling the power amplifier circuit. The gain also controls the final output power.

Figure 3-11 Typical gain control schematic

3.7. Temperature detection

The temperature detection function is used in many of Ralink's solutions, but it has not been seen in Atheros's solution. This function can detect the temperature of the power amplifier chip and prevent the chip temperature from overheating and burning. Another more important role is to adjust the output power of the power amplifier circuit according to the ambient temperature. In many cases, the change in ambient temperature will have a relatively large impact on the output power of the power amplifier chip. If the wireless transceiver knows the current temperature through the temperature detection circuit and adjusts its output power or changes the gain of the power amplifier properly, It is possible to maintain a stable power output of the power amplifier circuit when the ambient temperature changes, which is beneficial for improving the stability of the product.

Figure 3-12 shows a typical temperature sensing circuit for Ralink. RT1 in the figure is a thermistor. When the ambient temperature changes, its resistance changes. So, it is obvious that the value of TMP_DET will change, so that the transceiver can detect the temperature of the environment. The temperature sensing circuit is typically placed near the power amplifier chip.

Figure 3-12 Ralink commonly used temperature detection circuit

3.8. Completely designed power amplifier circuit

In the above, we discussed the various components of the power amplifier circuit. Now, let's combine these parts together to complete the design of the power amplifier circuit, as shown in Figure 3-13. Let's take a look, try to find out the previous parts, if you can, then you have a basic understanding of the general power amplifier circuit architecture of Wi-Fi products.

Usually, a reference design will be given in the data sheet of the power amplifier chip, which has a certain guiding effect on our design.

Figure 3-13 Completely designed RF power amplifier circuit

Chapter 4. Low Noise Amplifier

低噪声放大器在框图1-1中位于收发切换器（Transmit/Receive Switch）和无线收发器（Radio Transceiver）之间，对天线感应到的信号进行放大，这样才能使无线收发器进行有效的处理。可以说，低噪声放大器的性能直接影响着整个设计的灵敏度。

低噪声放大器的框图如图4-1所示，有四个部分组成，输入回路，输出回路，放大电路，增益控制，在以下的内容中，我们将逐个讨论。

图4-1 低噪声放大器的框图

4.1. 低噪声的放大器的主要参数

低噪声放大器，顾名思义，就可以知道其具有极低的噪声系数。噪声系数的物理含义是：信号通过放大器之后，由于放大器产生噪声，使信噪比变坏；信噪比下降的倍数就是噪声系数。

除了噪声系数以外，以下几个参数也是我们需要关注的：

功率增益

增益平坦度

工作频带

动态范围

功率增益主要就指低噪声放大器的增益能力，增益平坦度描述放大器在工作频带内频率变化引起的功率增益的波动，工作频带就是指放大器的正常工作的频率范围，动态范围是指放大器允许输入的最小和最大功率范围。

4.2. 低噪声微波器件的选择

芯片或者晶体管（场效应管）的选择，以下简称微波器件的选择，往往对于低噪声放大器的设计起着至关重要的影响。我们先来看一看在我们公司的设计中，通常选用什么微波器件。表4-1和表4-2给出了Atheros和Ralink常用的低噪声放大器微波器件。

我们不难发现，这些器件的选择没有太多的共性，我们能看到有四种解决方案，第一种是采用微波三极管来实现，第二种是使用专用低噪声放大器芯片，第三种是集成在前端模块（Frontend Module）中，第四种就是不使用低噪声放大器。我们在这里只讨论采用晶体管和专用芯片的方法。

表4-1 Atheros常用的低噪声放大器微波器件

微波器件（晶体管或芯片）的参数，基本上就决定了低噪声放大器的性能，我们来看一下最常用的SGA-8343的参数，如图4-2所示。图中给出的参数包括最大增益，噪声系数，S21，工作频率，供电电压，消耗的电流等等。对于专用的低噪声放大器芯片，参数也基本如此，在这里我们就不详细说了。

图4-2 SGA-8343的参数表

4.3. 输入回路

和功率放大器一样，低噪声放大器的输入回路中也会有匹配网络，但是Atheros好像是不走寻常路，很少看到低噪放的输入匹配网络，而Ralink则不一样，几乎在每个设计中都中规中矩的使用Π型匹配网络，如图4-3所示，就是Ralink常用的Π型匹配网络，我个人是比较推崇这种做法的。有了匹配网络，我们可以最大限度的保证我们的设计是高性能的，也就是High-Performance。

图4-3 Ralink常用的Π型匹配网络

4.4. 输出回路

和输入回路一样，输出回路通常也会放置匹配网络，同样，Atheros一般还是不这样做，他们最多会放置一个专有的印制带通滤波器（Printed Band Pass Filter），Ralink的输出回路上的Π型匹配网络基本上会输入回路上的一致，在这里不给出具体的形式了。

4.5. 电源与增益控制

增益控制的作用是很明显的，当接收到的信号强度较低时，我们可以提高低噪声放大器的增益，保证信号可以正常被接收；当接收信号的强度较高时，可以降低低噪声放大器的增益，以免造成信号阻塞。这就是所谓的自动增益控制（Auto Gain Control，AGC）同样，这对于提高产品的稳定性，是很重要的。

我为什么要把电源与增益控制放在同一节呢？因为低噪声放大器的增益是依靠改变供电电压来实现的，这样就很容易理解了。学过模拟电路的都会知道，三极管放大电路的放大倍数和供电电压有密切关系，对于芯片说也同样如此。图4-4给出了常见的增益控制的电路形式。图中的LNA_GAIN既是来自无线收发器（Radio Transceiver）增益控制信号，又是低噪声放大器的供电电源，C104是滤波电容，显而易见，低噪声放大器的增益直接与LNA_GAIN的电压有关。

图4-4 常见的增益控制的电路形式

4.6. 完整设计的低噪声放大器

在这里，我要向大家展示的是一款设计十分细腻的低噪声放大器，这也是我见过的设计最为优秀的低噪声放大器，就是来自某实际案例中的2.4GHz频段的放大器，让我们来一同领略它的风采，如图4-5所示。

图中的LNA_GAIN是来自无线收发器（Radio Transceiver）的增益控制信号，放大器使用的晶体管就是最常用的SGA-8343，R238，R239，R240是基极的偏置电阻，C219，L20，C220组成了低通滤波器，来自切换芯片（Switch）的LNA_IN通过低通滤波器之后经由C218耦合至低噪声放大器，Q2与C221，L51，C214，R240，C210，R239，R238，C211，R241，C215，L52组成了共射极放大电路，最终输出RFIN送至收发器进行处理。

尤其值得我们注意的是，在每一个节点处，都放置了滤波电容，这样，就可以最大限度的消除任何可能的噪声，从而实现性能优秀的低噪声放大电路。

图4-5 某实际案例中设计精良的低噪声放大器

第5章. 收发切换电路

收发切换电路实现的功能就是进行发射与接收的切换，通常其最重要的组成部分就是一颗芯片，我们分成四个部分来讨论：芯片的选择，发射与接收回路，天线回路，控制管脚的处理。

5.1. 切换芯片的选择

切换芯片在结构上，通常就是一个单刀双掷的开关，开关掷向哪一边决定于加在控制管脚上的电压。切换芯片的典型内部结构如图5-1所示。

图5-1 切换芯片典型的内部结构

在选择切换芯片时，我们主要关注以下几个参数：

working frequency

切换速度

关断的隔离度

导通的衰减

能够承受的功率

控制电压

功率消耗

有一个比较奇怪的现象时我们很少看到在Datasheet中提到切换速度这样的参数。在绝大多数设计中，几乎无一例外的使用了NEC公司的uPG2179作为切换芯片（Switch），其典型参数如图5-2 所示。

图5-2 切换芯片的典型参数

5.2. 发射与接收回路

切换芯片位于靠近天线的地方，决定着天线作为发射天线还是作为接收天线。功率放大器和低噪声放大器都会直接与切换芯片相连，这样，发射与接收回路上的匹配就是必不可少的。关注一下Atheros和Ralink的方案，会发现，Atheros会在发射回路上放置Π型匹配网络，但是Ralink则不会，一般就是通过电容直接耦合。

如图5-3所示，就是Atheros的典型发射与接收回路SW10就是那颗切换芯片。LPF_OUT是来自功率放大器的输出信号，R186，C121与R194组成了Π型匹配网络，LNA_IN是送至低噪声放大器的信号，SWITCH_TX与SWICTH_RX这两个信号的组合就控制着是打开发射通路还是打开接收通路。

图5-3 Atheros的典型的发射与接收回路

5.3. 天线回路

在5-4中我们已经看到，在Atheros的方案中，会在天线回路中放置一个印制滤波器（Printed Filter），图中的PF1就是Atheros专有的印制滤波器。同样，Ralink一般也不会在天线回路中设置滤波器或匹配电路。

5.4. 控制信号的处理

我们已经知道，图5-4中的SWITCH_TX和SWITCH_RX是来自无线收发器（Radio Transceiver）的控制信号，是直流电压，这样，为了稳定这个电压值，避免造成切换器的误动作，我们一般会在控制通路上串联一个电阻（或电感），一般是小于1K的电阻，并且在控制管脚的位置放置滤波电容（1-10pF），这样，我们就可以很好的保证切换芯片没有误动作，从而，我们就得到了如图5-4所示的完整的切换电路的设计。

图5-4 完整设计的切换电路

第6章. 天线与天线连接器

在这一章里，我要讲的不是天线的设计，因为目前我还不太懂天线设计，而且天线设计是一个十分专业和复杂的学科。在这里我想要说的其实就只是一个问题：一定要在天线或者天线连接器的附近放置一个Π型匹配网络，这一点是我们做射频设计的人必须要牢记的事实。看一下Atheros 和Ralink的方案，会发现Π型匹配网络是必不可少的，典型的设计如图6-1所示。

图6-1 典型的天线连接器电路设计

第7章. 完整设计的射频电路

在前面几章的内容中，我们分成五章分别讲解了射频电路的无线收发器（Radio Transceiver），功率放大电路（Power Amplifier，PA），低噪声放大器（Low Noise Amplifier，LNA），收发切换电路（Transmit/Receive Switch），天线与天线连接器（Antenna And Connector），在每章的最后一节，我们都给出了每一部分的完整设计。我想你已经知道了——没错，只要把我们每个部分的完整设计组合在一起，那么我们就得到了Wi-Fi产品的一般射频电路的完整设计，我们不要急，我们再来回顾一下在本文一开始提到的射频设计框图，如图7-1。相信大家这时一定已经可以把每一个部分细化，得到更加详细的射频设计框图。

图7-1 射频设计框图

通过前面的讨论，我们已经知道，功率放大器是由带通滤波器，Π型匹配网络，功率微波器件，增益控制，供电电路，功率检测，温度检测低通滤波器这些部分组成的；低噪声放大器是由Π型匹配网络，低噪声放大电路和增益控制组成的；收发切换器是由Π型匹配网络，切换芯片，滤波器组成的；天线和连线连接器部分是由Π型匹配网络和连接器组成的。于是，我们得到了Wi-Fi产品一般射频电路的详细框图，如图7-2所示。

图7-2 射频设计详细框图

现在，让我们将各个模块的详细电路图，看看我们得到了什么。没错，我们得到了完整的设计图，如图7-3所示。在这个原理图中，我们设计的是一收一发的情况，如果是二发二收，那么原理图就是两个图7-3，复制而已。

图7-3 完整详细的原理图

由于时间有限，编写者水平更加有限，错误之处在所难免，欢迎大家批评指正。

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