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Abstract: This paper presents a new set of vehicle multimedia system design based on ADSP-BF561 embedded multimedia processor designed by American Analog Devices (ADI) to support embedded audio and video applications, GPS, GPRS, HFCK, network port, USB, CAN bus, I2C control and mass storage functions are powerful multimedia systems, especially suitable for in-vehicle environments, and can also be used as personal digital assistant applications.Keywords: digital signal processor; multimedia information processing; automotive electronics; embedded system
system introduction
The ADSP-BF561 processor is a new high-performance product for multimedia and communication applications from Analog Devices. It has a rich peripheral interface and integrates two Blackfin processor cores. Each core contains 2 multipliers/ Accumulator (MAC), two 40-bit arithmetic logic units (ALU), four video ALUs and one 40-bit shifter. The processor combines a dual multiply accumulator processing engine, RISC instruction set and single instruction multiple data (SIMD) capabilities to form a unique instruction set architecture. In addition, two parallel external interfaces (PPIs) are integrated internally to provide a system-level on-chip solution for simultaneous image acquisition, processing and display. The structure is shown in Figure 1.
Figure 1 Block diagram of ADSP-BF561
The system scheme proposed in this paper is to expand the audio, video processing system, network port solution, CAN bus, GPS, GPRS, HFCK and other functions with the ADSP-BF561 processor as the core, and integrate the communication, entertainment and security control into the vehicle multimedia. system. The audio part includes audio acquisition, processing and playback functions, assisting HFCK to complete high-quality in-car hands-free communication; video part includes video surveillance and video playback, while meeting people's entertainment and security control requirements; CAN bus provides on the car Unified control of the control part; the network port and USB interface provide high-speed and convenient data exchange capability between the system and peripherals. The system structure is shown in Figure 2.
Figure 2 System structure
System design
Audio function design
ADI's AD1836A is a high-performance, single-chip audio encoding and decoding chip that provides four ADC conversion channels to form two input stereo channels; six DAC conversion channels to form three output stereo channels; He also has a SPI port, the processor can be used to rewrite the control register of the AD1836A, set the ADC conversion sampling rate, signal gain and other parameters to meet the practical application requirements. The AD1836A sampled digital audio output and the digital audio input to be played back are exchanged through the synchronous serial port and the processor. This can be seamlessly connected to the ADSP-BF561's synchronous serial port. The ADSP-BF561's synchronous serial port support A variety of serial protocols provide a seamless connection to the processor and various synchronous serial peripherals. The connection between ADSP-BF561 and AD1836A is shown in Figure 3.
Figure 3 audio part schematic
Video part design
People inevitably encounter many emergencies in driving. For example, when a car is suddenly coming back, there is a sudden coming from a car. When driving at a high speed, there are suddenly people or vehicles coming from the side. Such situations are generally handled by people, and emergency braking is performed. However, there is a long delay and it is easy to cause a traffic accident. To this end, a video acquisition system is installed in some in-vehicle systems, and the processor monitors a certain range of states around the vehicle body and performs emergency operations to shorten the delay and improve driving safety. However, most of these systems currently cannot combine video surveillance and video entertainment systems. The root cause is that the processor has only one PPI interface and cannot perform body monitoring and video playback at the same time. The ADSP-BF561 embedded multimedia processor used in this system has two independent PPI interfaces, which can simultaneously perform image acquisition and video playback. The video part is shown in Figure 4.
Figure 4 video part schematic
CAN bus, USB interface and I 2 C control design
CAN bus controller design
The CAN control interface is widely used in various control parts of the car. In order to control each part, the CAN bus controller is designed in the system. It uses the CAN bus controller SJA1000 chip from Philips, and it supports the CAN2.0 protocol. The SJA1000 controller adopts the address data multiplexing mode. In the address period, it controls the SJA1000 to latch the addresses on D0~D7 through the address latch signal ALE. To avoid interference between multiple devices in the asynchronous space 2, the address of the BF561 is used. Lines A2 and nAMS2 are decoded as address latch signal ALE, and A2 and nAMS2 are used to generate chip select signal nCS through different decoding logics, nARE and A2 are decoded by BF561 to generate nRD signals, nAWE and A2 are decoded to generate nWD. Signals, so that they meet the SJA1000 read and write timing requirements, its read and write logic truth table is shown in Table 1.
CAN bus is applied to the field control, the interference is strong, and the data transmission adopts differential mode transmission. Therefore, the serial transmission and reception signal of SJA1000 is converted into differential mode by the conversion interface PCA82C250 to enhance the anti-interference ability. When the processor is to issue a command to a device on the CAN bus, the command data is written into the send buffer of the SJA1000 controller, wherein the first two bytes mark the send address and the number of bytes of the command data, and the controller outputs the information. Converted to serial output to the CAN bus, the device on the bus determines whether to receive and respond to the command based on the address information.
USB interface and I 2 C control design In order to support plug-and-play devices and facilitate data exchange between peripherals and systems, we have designed a USB interface in the system. The selected control chip is SL811HS introduced by CYPRESS. A USB control chip that supports embedded applications, supports master/slave mode and full-speed (12Mb/s), low-speed (115Mb/s) communication. When working in master mode, it supports 1.1 protocol when working in slave mode. Under, support 2.0 protocol, but does not support high-speed transmission. The I 2 C control part uses the Philips I 2 C bus PCA9564 controller, which supports data transmission and reception in master-slave mode. The processor controls the devices on the I 2 C bus by reading and writing the contents of its four internal registers.
Network port design
The design uses the LAN91C111 chip of the Ethernet controller of Standard Microsystems Corporation (SMSC). It is mainly used for the network port solution of embedded applications. It has a memory management unit inside, which can effectively allocate memory dynamically and reduce the work of the processor. Support synchronous and asynchronous transmission, we will connect it to the asynchronous space 1 of the processor. His main signals are address signals A1 ~ A15, data signals D0 ~ D31, address enable signal ALE, byte enable signals nBE0 ~ nBE3, reset signal Reset, interrupt request signal INTR, read and write enable signals nRD and nWR, He supports 8-bit, 16-bit and 32-bit data transfers, controlled by byte enable signals nBE0~nBE3. The connection scheme between the network port and the processor is shown in Figure 5.
Figure 5 network port schematic
GPS, GPRS, HFCK design
GPS, GPRS, and HFCK functions are realized by externally connecting Siemens' latest ultra-compact GPS/GPRS combination module on the UART interface of BF561. It integrates 3-band (900/1800/1900MHz) GSM/GPRS and GPS satellite navigation receivers. Its all-in-one design (allonboard) allows users to use GPS for satellite positioning while using GPRS/GSM functions to implement GPRS, voice, fax, SMS and other communication functions. The GPS part sends the received satellite signal to the processor through the UART port, and in combination with the map data, the user can obtain real-time accurate position information; the HFCK function in the system receives the voice signal through the GPRS/GSM part, after the audio is collected. Perform noise cancellation and echo cancellation to get better call results. The scheme is shown in Figure 6.
Figure 6 GPS/GPRS part schematic
Conclusion
The ADSP-BF561 processor is the latest addition to Analog Devices' Blackfin family of products. It extends the external addressing space on top of the BF531/2/3, enabling 32-bit external data exchange and providing more programmable pins. In particular, the integration of two cores and PPI video processing interface, all these advantages provide superior conditions for the design of complex multimedia systems with powerful sound collection, video processing, security control and entertainment. I believe the ADSP-BF561 processor These advantages will soon be revealed in other applications.
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